Display IP Design Verification Engineer - 106782

Location: Austin, Texas, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

Display IP Design Verification Engineer

The Role:

The Display Controller team within the Radeon Technologies Group(RTG) is looking for an individual to participate in the design verification of the Display IP!

The Person:

The candidate would participate on a team of design verification, architects and design engineers, working closely with other team members to understand and verify the functionality of the design within the context of the unit, block, and overall system. The candidate would be responsible for carefully detailing and executing test plans consisting of directed and random tests to be run under simulation and hardware acceleration. Experience with hardware modeling, assertions, and formal verification methods are valuable assets. The candidate would be encouraged to adopt evolving verification methodologies used in the industry as well as develop custom techniques to functionally verify increasingly complex IP designs within results-oriented schedules.

Key Responsibilities:

  • Join in the development of leading-edge display technologies and understand the architecture of the Display IP and functional blocks being designed.
  • Use advanced verification methodologies for the verification of sophisticated designs
  • Own and execute on verification of a sizable design by applying UVM verification methodology
  • Work with existing tools/flows or develop new tools/flows to complete the assigned verification task.
  • Compose test and coverage plan, and validation vectors to ensure functional completeness
  • Build SystemVerilog and/or C/C++ models and test sequence libraries for simulation
  • Build a test bench and monitors for DUT
  • Debug function/performance bugs of Display IP

Preferred Experience:

  • Proven understanding in ASIC IP verification methodologies and processes
  • 5+ years of experience in ASIC verification
  • Must be proficient in Verilog and System Verilog language
  • Must be good at C/C++ programming, and working in Linux and Windows environments
  • Must have ASIC design knowledge and be able to debug Verilog RTL code using simulation/emulation tools
  • Must have ASIC design verification experience in test plans, test creation, and triage, coverage and assertion, etc.
  • Must be proficient of script language like Perl, Python
  • Must have excellent writing and communication skills
  • Must demonstrate strong analytical thinking and problem-solving skills with excellent attention to detail
  • Must have good collaboration and interpersonal skills

Academic Credentials:

BS + 5 years or MS + 3 years or PhD + 1 years of Electrical Engineering and/or Computer Architecture work experience.


Requisition Number: 106782 
Country: United States State: Texas City: Austin 
Job Function: Design


AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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