RTL Design Engineer Lead - 125563

Location: Roseville, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

The Role:

The Memory IO team is looking for a hardworking and experienced Design Engineering Lead for RTL and Firmware development of high-speed LPDDR, DDR and inter-chip IO IPs. We are looking for someone to be a part of the definition, design, and development phase of industry-leading Memory PHYs and interface IP. This opportunity includes creation of new IO designs (microarchitecture, design, team leadership) as well as working on multiple designs and improving methodologies in parallel.

Join us and be a part of a team that delivers Industry leading IP and help our specialists in RTL, FW, circuit, and architecture teams develop groundbreaking and differentiating IPs!


The Person:

The ideal candidate will have strong analytical/problem-solving skills and pronounced attention to details. To be successful you will need to be a self-starter and be able to independently drive tasks to completion. The ability to build positive relationships is key as you will interact with multiple multi-functional teams.


Key Responsibilities:

  • Lead a team of RTL designers for memory I/O
  • Micro-architecture of digital blocks for memory IO, hardware/firmware partitioning
  • Digital design and RTL coding
  • Direction and supervision of other RTL and firmware designers
  • Definition and optimization of training hardware and algorithms including optimization in silicon
  • Working with internal customers to define functional boundaries and specs


Preferred Experience:

  • Digital design engineering experience with successful tape-outs and technical leadership
  • Knowledge of Verilog, C, C++ and a scripting language; experience with Python, Perl and TCL.
  • Knowledge of clocking architectures, synchronization, and CDC methodology
  • SERDES, DDR, Memory Controller, or MAC Design experience is preferred
  • Strong understanding of computer organization/architecture
  • Firmware Development experience
  • Mixed signal RTL experience
  • Experience with low level, physical phenomena-oriented logic design is an asset (dealing with IO, clocking, voltage control, etc.)
  • Laboratory experience, including the use of equipment: oscilloscopes, logic analyzers, etc.


Academic Credentials:

  • Bachelor's degree in Electrical or Computer engineering, Master's or PhD degree is a plus.


Location: Boxborough, MA, Austin, TX, Santa Clara, CA




Requisition Number: 125563 
Country: United States State: California City: Roseville 
Job Function: Design
Hiring Manager: Damon Tohidi


AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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