Post Silicon Validation Engineer

Title : Post Silicon IP Validation Engineer

The Role:

The AMD IP Systems Engineering Team is on the lookout for a dynamic, energetic, PCIe PHY Systems Engineer to join our growing team.

As a key contributor to the success of AMD's IP and SOCs, you will be part of a leading team to drive and enhance AMD's abilities to deliver the highest quality, industry leading technologies to market. The Systems Engineering team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

The Person : Will have the following attributes to be succesful in this role

• Must have excellent written and verbal communication skills
• Must excel in a dynamic team working environment
• Leadership and mentoring skills a definite asset
• Must be a self-starter and be able to independently drive tasks to completion
• Ability to be flexible in terms of responsibilities

The Person : 

Responsibilities :

As a PCIe PHY Systems Engineer, you will drive the planning, verification, and debug of various hardware IP as well as supporting the debug and functional tests of the PCIe PHY and its interfaces with other hardware IP for forthcoming AMD APU, CPU, Compute and Discrete Graphics SOC programs.

Responsibilities include:

• Defining, documenting, executing and reporting the overall functional test plan and verification strategy for a set of AMD IP and SOC's
• Driving technical innovation to enhance AMD's capabilities in IP validation/verification, including tool and script development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives.
• Supporting the debug of PCIe PHY IP issues found during post-silicon, bring-up, validation, and production phases of SOC programs
• Lab-based silicon bring-up and unit test execution focused on the Physical and PCS layer hardware and firmware functionality, while also extending to the protocol layer of the PCIe stack
• Low-level testing of PCIe hardware features using diagnostics, software tools, protocol/logic analyzers, oscilloscopes and other test equipment.
• Engaging in system-level debug/triage efforts involving PCIe PHY.
• Leading collaborative technical discussions to drive resolution on technical issues and roll out technical initiatives
• Continuous improvement and developing knowledge of CPU and GPU system architecture/debug and other internal IPs
• Supporting issues on customer platforms as requested by customer support teams

Preferred Experience & Skill set:

• Experience in high speed IO SERDES (PHY) design/validation; verification or post-silicon verification.
• Extensive knowledge of the physical and protocol levels (PIPE I/F, PCS ,MAC) of one or more common high-speed interfaces is an asset.
• Extensive experience with board/platform-level debug, including clock/power delivery, sequencing, analysis, and optimization
• Strong programming/scripting skills (eg. C/C++, Perl, Ruby, Python)
• Extensive experience with ASIC debug techniques and methodologies
• Extensive experience with common lab equipment, including protocol/logic analyzers, oscilloscopes, etc.
• In-depth knowledge of PC architectures an asset

Education : Bachelors or Masters in Electrical or Computer Engineering

*LI-AP1