Senior Verification Engineer - UVM Testbench - 78299

Location: Austin, Texas, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

 

ASIC IP Functional Verification Engineer

 

THE ROLE:

The focus of this role is to plan, create, and maintain the UVM testbench used to verify new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.

 

THE PERSON:

  • An analytical thinker with problem-solving skills and excellent attention to detail
  • Possesses excellent comprehension, communication, and interpersonal skills
  • Enjoys working in a fast-paced, multi-project team environment using state of the art tools and technology

 

KEY RESPONSIBILITIES:

  • Collaborate with architects, hardware engineers, and firmware engineers to understand the new features being implemented, create test plans and functional coverage metrics.
  • Plan and implement the UVM testbench, functional coverage model and assertions.
  • Participate in debugging failing verification tests to determine if the root cause is an error in the RTL, verification model, or the test.  Fix all identified failures in the verification model.
  • When appropriate verify low power design features at the subsystem level using power-aware verification technique and formal verification.

 

PREFERRED EXPERIENCE:

  • 10 or more years of experience with UVM like verification methodology
  • Knowledge of ASIC Verilog design and functional modeling
  • Proficient in using UVM test benches. Five years or more experience on a complex UVM project.
  • Experience with Assertion and Functional Coverage
  • Proficiency in debugging RTL code using simulation tools
  • Programming in C/C++ for modeling and stimulus generation is a plus.
  • Power-Aware UPF based experience is a plus
  • Performance Verification experience is a plus
  • Formal Verification experience is a plus
  • Graphics pipeline knowledge a plus

 

ACADEMIC CREDENTIALS:

  • BS/MS/Ph.D. degree in Electrical Engineering, Computer Engineering

LOCATION:

This position is located in Austin, TX


AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability or any other characteristic protected by law. EOE/MFDV

 

#LI-PH1



Requisition Number: 78299 
Country: United States State: Texas City: Austin 
Job Function: Design
  

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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