Silicon Design Engineer 2 - 82521

Location: Austin, Texas, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

UMC Verification Engineer

The Role:

We are looking for an innovator and hardworking verification engineer to join our team! Someone that can work in a fast pace environment and able to thrive on new challenges.

We have competitive benefit packages and award-wining culture. Join us!

The Person:

The person for this role would need good communication skills & analytical thinking skills to be successful. Also, should have the ability and desire to foster a team environment.

Key Responsibilities:

As a functional verification team member, you would:

  • Provide technical expertise for developing the functional verification strategy of AMD's next generation of Dram Controller (also known as UMC).
  • Maintain and enhance existing verification infrastructure.
  • Develop new test plans, functional coverage points, and test bench components like test-cases, monitors, scoreboards, sequencers, and sequences.

AMD uses IP-XACT methodology. UMC integrates the ddr phy into our IP and also integrates the UMC IP into each Client and Server SOC.

Daily activities include:

  • Looking at the RTL to find functional bugs,
  • Working with the RTL team to fix the bugs,
  • Reading the DRAM Controller MAS(Micro-architectural Spec) and Jedec Guidelines
  • Developing test plans, functional coverage points, monitors, scoreboards, sequencers, and sequences, which utilize scripts, System Verilog, UVM, DFT, and methodologies to increase the rate with which bugs are found and resolved.

The role generally entails a mixture of:

  1. Ownership of a piece of our test bench,
  2. Planning & execution of feature additions and
  3. Next dram feature enablement using coverage.
  4. Bug fixes
  5. debug of regression signatures

Preferred Experience:

  • Solid understanding in Object Oriented programming and debug skills.
  • Exposure and experience in Verilog and System Verilog (or some Object-Oriented Programming like C++)
  • Knowledge in scripting languages like Perl, and logic simulation.
  • Strong communication skills and the ability to work independently as well as in a cross-site team environment.
  • Proven technical expertise in functional verification of complex designs including test planning, test bench development, stimulus generation, checking, and functional coverage is a plus.
  • Knowledge with OVM or UVM is a plus.
  • Experience with memory controllers, memory models (ddr4, lpddr4), Jedec and/or ddr phys is a plus.

Academic Credentials:

MS in Computer Engineering or education/experience BS in EE or Comp Eng and proven experience in Functional Verification experience.

Location:

Austin, TX

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Requisition Number: 82521 
Country: United States State: Texas City: Austin 
Job Function: Design
  

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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