ASIC Front-End Design Engineer - 115084

Location: Austin, Texas, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

ASIC Front-End Design Engineer - New Graduates

 

THE ROLE:
The Display IP Team is the team behind such ground-breaking visualization technologies as: FreeSync, FreeSync-HDR, AMD Wireless Display, VR Ready, Liquid VR, and Eyefinity. We are also the team responsible for the display features within several generations of top-tier game consoles. As a member of our team, you will collaborate with innovative engineers and scientists who share your passion for technology. Many of them are former interns who have returned to our team after completing their graduate or undergraduate degrees. Innovation isn't easy, but their mentorship will help you push your skills to the next level. Work assignments that are challenging and cross-functional will enable you to expand your professional network while building a legacy at one of the best semiconductor companies to work for.

The Display IP team is responsible for researching, developing, and delivering its hardware designs to all discrete GPUs, APUs and custom SOCs within AMD. This single department develops the custom hardware needed to process and deliver graphics from memory to screen. This includes a breadth of processing tasks including memory fetching, quality of service, pixel and image processing, compression, decompression, and output encoding using standards such as HDMI and DisplayPort. As a member of our growing team, you will have an opportunity to collaborate with our architects, designers, verification engineers, and managers to perform digital hardware design and verification functions. The Display IP Austin is a new team starting to work on an exciting new Video Processing Engine. We have a vibrant culture that focusses on collaboration and teamwork. We offer flexible hours and a flexible work environment with opportunities to work both in-person and remotely. If you are passionate about technology and you're looking to grow as an individual and as a member of a team, then we welcome you to join us.

 

THE PERSON:

To aid the Display IP team in delivering world-class, cutting-edge designs to AMD’s product portfolio through the application of industry-leading tools/flows, and processes. A talented FEINT engineer with records of technical ownership and execution to drive synthesis, formality, lint, cdc, and PPA analysis from assignment to completion. A forward-thinking engineer who tends to optimize/improve the workflow, anticipate/analyze/resolve technical issues, and enjoy a competitive pace. A strong written and verbal communicator with strong problem solving and attention to detail skills along with professional interpersonal communication capability.

 

KEY RESPONSIBILITIES:

  • Work closely with design team members to deliver high quality RTL that meet all the key metrics of Lint, CDC, Timing, Area, and Performance
  • Run all the synthesis, formality, CDC and Lint flows and provide weekly status update to the team
  • Develop RTL synthesis strategy and scripts to perform synthesis and PPA analysis (performance, power, area) on subsystem level and block level RTL designs to drive for continued improvement of QoR (quality of result)
  • Develop, adopt and automate RTL design rule checks in collaboration with Back-End Integration and Physical design teams, triage and debug design rule violations with the RTL design team

  

PREFERRED EXPERIENCE:

  • Strong understanding of digital electronics, ASIC design flow, and RTL design
  • Strong knowledge of FE design tools such as Design/Fusion Compiler, CDC, Lint, Prime Time, Power Artist, etc.
  • Familiar with Verilog, C/C++ and other scripting languages (e.g. Tcl, Perl, Python and Makefile)
  • Excellent skills with Unix/Linux environment
  • Familiar with RTL coding techniques for competitive PPA-measured QoR
  • Familiar with RTL coding style for clean check on design rules (LINT, CDC, etc.)
  • Good understanding of gate level circuit design and physical level design concept and methodology
  • Familiar with VCS/Verdi and SPG based (dynamic/static) verification environment
  • Strong knowledge of scripting Linux/Unix environment, Perl, and TCL are preferred.
  • Excellent communication skills (both written and oral)
  • Self motivated, and committed to achievement

 

ACADEMIC CREDENTIALS:

  • BS/MS in computer engineering, electrical engineering, or related.

 

LOCATION: 

Austin, TX

 

 

#LI-GV1



Requisition Number: 115084 
Country: United States State: Texas City: Austin 
Job Function: Design
  

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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