Silicon IP Validation Engineer

Location: Austin, Texas, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

Title : Silicon IP validation Engineer


The Role:

We are seeking a Serdes PHY Systems Engineer. In this role you will drive the planning, silicon validation, and debug of various hardware IP. In addition this role will be supporting the debug and functional tests of the Serdes PHY and its collaboration with other hardware IP for forthcoming AMD APU, CPU, Compute and Discrete Graphics SOC programs.

The Person:

The ideal candidate will have the following attributes:

  • Hardworking innovators who collaborate well with a variety of teams
  • Strong analytical/problem solving, statistical analysis and attention to details
  • Must be a self-starter and be able to independently drive tasks to completion
  • Ability to be flexible in terms of responsibilities

Key Responsibilities:

  • Characterize and validate mixed-signal Serdes IP. Responsibility includes defining, detailing, executing and reporting the overall test plan
  • Supporting the debug of Serdes IP issues found during post-silicon, bring-up, validation, and production phases of SOC programs
  • Lab-based silicon, electrical measurements, and unit test execution of a Phy IP
  • Develop/give to diagnostic framework including FW for IP training, margining, and debug
  • Low-level testing of I/O and PHY hardware features using diagnostics, software tools, protocol/logic analyzers, oscilloscopes, and other test equipment.
  • Engaging in system-level debug/triage efforts involving Serdes PHY.
  • Driving technical innovation to improve AMD's capabilities in IP validation/verification, including tool and script development, automation and testing capabilities, technical and procedural methodology improvement, and various internal and multi-functional technical initiatives.
  • Leading collaborative technical discussions to drive resolution on technical issues and roll out technical initiatives

Preferred Experience:

  • Experience in high-speed I/O Serdes design and/or post-silicon validation
  • Strong programming/scripting skills (eg. C/C++, Perl, Ruby, Python)
  • Familiarity with Unix/Linux OS as well as Windows
  • Lab experience testing and debugging Phy analog circuits
  • Experience with common lab equipment, including oscilloscopes, BERT, Spectrum Analyzer, VNA, TDR, logic analyzers, etc.
  • High-speed I/O SerDes design knowledge, understanding of CDR, bandgaps, PLLs and DLLs
  • Solid understanding of basic computer architecture.
  • Knowledge of the physical and protocol levels (PIPE I/F, PCS, MAC) of one or more common high-speed interfaces is an asset
  • Experience with board/platform-level debug, including clock/power delivery, sequencing, analysis, and optimization

Academic Credentials:

  • Bachelors or Masters in Electrical or Computer Engineering


  • Austin, TX


Requisition Number: 146064 
Country: United States State: Texas City: Austin 
Job Function: Design


AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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