DFT DV Engineer

Location: Bangalore, Karnataka, IN

Company: Advanced Micro Devices

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What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

 

Key Responsibilities:

· Working with a multi-discipline and international team of engineers on design-for-test (DFT) architecture, design, tools and methodology initiatives

· Performing scan insertion, ATPG verification and test pattern generation

· Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design

· Performing DFT RTL design per micro-architectural specifications using design generation flows

· Performing DFT RTL integration, synthesis, equivalency checking, timing analysis and closure including defining design constraints

· Writing and maintain DFT documentation and specifications

· Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis

 

Preferred Experience:

· Minimum 5 years of ASIC design experience

· Demonstrated technical leadership and works well with cross-functional teams

· Excellent communication and interpersonal skills

· Experience in complex ASIC design (multi-million gates) in DFT/DFD techniques such as JTAG/IEEE standards, scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic, testing of high speed SerDes IO and analog design

· Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential

· Understanding various technologies that must work with DFT/DFD technology such as CPU’s, graphics engines, high-speed digital design, memory and I/O controllers, … etc

· Working knowledge and experience in verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations

· Experience in solving logic design or timing issues with integration, synthesis and PD teams

· Good working knowledge of UNIX/Linux and scripting languages (e.g., TCL, c-shell, Perl), C++ programming

· Knowledge in EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis

· Knowledge of ATE and digital IC manufacturing test is a plus

· Knowledge in using emulator for ATPG pattern verification is a plus

Academic Credentials:

· Minimum Bachelors in Electrical/Electronics or Computer Engineering (or equivalent). Preffered Masters in VLSI/Computers/Electronics

 

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Requisition Number: 104748 
Country/Region/Location: India State/Province: Karnataka City: Bangalore 
Job Function: 
Design  

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