DFT Flow methodology lead

Location: Bangalore, Karnataka, IN

Company: Advanced Micro Devices

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What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

 

 

THE ROLE:

  • As a member of the S3 SoC DFT Team, the successful candidate will own/lead the DFT Flow Methodology, architecture and implementation including SCAN, ATPG, MBIST, BSCAN.
  • Position includes DFT flow creation/development, data analysis and silicon debug of DFT in leading edge process technologies. 
  • Strong self-driving ability, should have excellent communication skills (both written and oral)
  • Strong problem-solving skills

 

KEY RESPONSIBILITIES:

 

  • Working closely with the DFT Architecture and the various IP Design teams to align on the DFT requirements and successfully implementing the DFT flow and methodology.
  • Design and develop new DFT Flow and/or DFT verification methodologies and flows for IPs and system on a chip (SoC)
  • Working closely with the RTL designers, Verification Engineers, and PD team to find creative ways to accelerate the identification of functional defects.

 

PREFERRED EXPERIENCE:

  • Experience and an understanding of ASIC DFT, synthesis, simulation and verification flow
  • Experience is End-to-End DFT flow development/creation.
  • Expert in Perl, Python, TCL, and ability to create complex flows/scripts.
  • Strong EDA tools experience (Tessent, Design Compiler, Spyglass,)
  • Experience in DFT architecture for complex chips
  • Experience in RTL development using Verilog/System Verilog having worked on RTL for IP and SoC integration
  • Proficient in doing basic unit-level verification using simulations.
  • Experience with RTL quality check tools/methodologies such as Spyglass, CDC, Lint is required.
  • Must have experience with integration of various IPs into complex SOCs.
  • Exposure to Static timing analysis & Timing closure is required.
  • Scan/ATPG patterns & test flows development, debug, test, and characterization
  • Excellent hands-on debug skills and scripting skills are critical.
  • Must have good communication skills and the ability to work in a worldwide team environment.
  • Knowledge & experience of low power concepts, clock gating, power gating is a plus
  • Experience with post-silicon bring up is a plus

 

ACADEMIC CREDENTIALS:

  • B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering
  • 10+  years’ experience in DFT design/Methodology

#LI-SB1



Requisition Number: 158632 
Country/Region/Location: India State/Province: Karnataka City: Bangalore 
Job Function: 
Design  

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