DFT Engineer (102944)

Location: Bangalore, Karnataka, IN

Company: Advanced Micro Devices

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What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

 

 

DFT Engineer

 

 

The Role:

  • As a key member of the SCBU SoC DFT Team, the successful candidate will play a significant role in ensuring the quality of next generation AMD SoCs through structural DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques.
     

The Person:

 

  • A successful person in this role would be able to work in a collaborative team environment working with the cross functional Engineers to find creative ways to accelerate the identification of functional defects.
  • Must have excellent communication skills (both written and oral) to work in a worldwide team environment.
  • Strong self-driving ability, Strong problem-solving skills 

 

 

Key Responsibilities:

 

  • Working closely with the Architecture team and the various IP Design teams to align on the DFT requirements and successfully implementing the DFT RTL at the SoC level
  • Generating high quality manufacturing test patterns for stuck-at, transition fault models and using on-chip test compression techniques
  • Set up DFT timing constraints, defining the overall SOC Test STA methodology.
  • Working with the Design team to clean-up all the DFT related constraint issues
  • Closely work with physical design team to generate and validate timing constraints
  • Developing, improving and maintaining automation scripts as necessary

 

 

Preferred Experience:

 

  • Experience in DFT architecture for complex chips
  • Exposure to Static timing analysis & Timing closure is required.
  • Proven experience in DFT constraints handling, Block and Top-level test mode Static timing analysis (STA).
  • Experience in SOC timing closure in DFT modes and sign-off
  • Experience with RTL quality check tools/methodologies such as Spyglass, CDC, Lint is required.
  • Must have experience with integration of various IPs into complex SOCs.
  • Scan/ATPG patterns & test flows development, debug, test and characterization
  • Excellent hands-on debug skills and scripting skills are critical.
  • Knowledge & experience of low power concepts, clock gating, power gating is a plus
  • Experience with post-silicon bring up is a plus
  • Any prior experience with microprocessor designs is a plus.

 

 

 

Qualification:

  • B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering with 8+ years of DFT Experience

 

 

#LI-GM1

 



Requisition Number: 102944 
Country/Region/Location: India State/Province: Karnataka City: Bangalore 
Job Function: 
Design  

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