SMTS Silicon Design Engineer

Location: Bangalore, Karnataka, IN

Company: Advanced Micro Devices

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What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

 

Responsibility:

1.           Work closely with SOC Architecture team for SOC clocks statistical timing target goals.

2.           Responsible for merging the IP level timing constraint to SOC level, maintain all SOC level clocks definition and exceptions.

3.           Responsible for full timing constraints delivery to Physical Design, timing constraints quality, check timing result, and update timing result.

4.           Responsible for working with Physical design and IP teams to close timing by fix timing constraint issues

5.           Responsible for SOC level timing constraints signoff and work closely with IP for timing constraints review and signoff.

6.           Collaborate with IP team to make sure the proper constraints are integrated and feedback any issues from SOC level.

7.           Understanding clock design requirements and make sure they are correctly setup in SDC.

 

Requirement:

1.           B.Tech/M.Tech/MS in Electrical/ Electronics Engineering or related technical areas

2.           More than 10 years working experience on SOC Implementation and Tapeout.

3.           Have strong knowledge with digital design timing signoff methodology.

4.           Familiar with STA(static timing analysis) methodology

5.           Familiar with timing target definition methodology

6.           Familiar with SOC architecture and design knowledge, such as Serdes, AXI buses, source synchronous and test design.

7.           Strong commitment to schedule and quality of the SDC delivery in project’s each milestone.

8.           Have experience on complex  SOC full chip timing constraints delivery and timing quality check

9.           Have good communication skills and be able to work both independently and in a team, can co-work with IP and PD team on the timing closure .

10.         Can lead a small team , 2~4 people , to deliver the tasks.

11.         Familiar with EDA tools: GCA (Galaxy Constraint Analyzer) , PT(Prime Time) , Fishtail

12.         Good teamwork and leadership skills

13.         Good script development skills

 

#L1-DC2



Requisition Number: 114043 
Country/Region/Location: India State/Province: Karnataka City: Bangalore 
Job Function: 
Design  

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