Physical Design Manager (92726)

Location: Bangalore, Karnataka, IN

Company: Advanced Micro Devices

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What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

 

Senior Physical Design Engineer

 

The Role:
In this role you will be given an opportunity to work on the next generation technology that will be part of future AMD Microprocessors powering Servers and Personal Computers as well as Graphics Cards and VR sets.  The DXIO FEINT/Implementation team is responsible for Synthesis, place & Route, Timing closure/CDC/LINT/DFx for very high speed (>2G) design with complex I/O clocking.

Responsibilities:

We are currently looking for a senior technical engineer who will drive all implementation aspects of DXIO, NBIO, & CIT next generation IPs.  The DXIO & CIT team deal with multiple I/O protocols including PCIe, SATA, Ethernet & Infinity Fabric link-layer.

This team is a group of highly experienced ASIC design engineers working on High speed (>2G) designs with very complex clocking infrastructures. The team owns implementation activities including Synthesis & DFT, floorplan, placement, clock tree synthesis, routing, STA

The team will work on cutting edge IP for these I/O protocols to achieve physical implementation with best PPA, including developing reference floorplans, implementation scripts for SoCs worldwide, and locally support SoC in Bangalore & Hyderabad.   

 

Preferred Experience:

Synthesis, Floor-planning, Placement, clock trees synthesis, Post Route Timing closure for high-speed >=2GHz designs.

CDC, PTPX, STA, LINT & DFT, IP, Physical design flow & scripting in TCL, Python 

 

Location: Bangalore India

 

 

 

 

The Role:
In this role you will be given an opportunity to work on the next generation technology that will be part of future AMD Microprocessors powering Servers and Personal Computers as well as Graphics Cards and VR sets.  The DXIO Implementation team is responsible for Synthesis/Timing closure/CDC/LINT/DFx for very high speed (>2G) design with complex I/O clocking.

 

 

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Requisition Number: 92726 
Country/Region/Location: India State/Province: Karnataka City: Bangalore 
Job Function: 
Design  

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