Lead DFT Engineer(SMTS- 173046)

Location: Bangalore, Karnataka, IN

Company: Advanced Micro Devices

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What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.


As a member of the Server SoC DFT Team, the successful candidate will own the DFT micro-architecture and RTL implementation using Verilog/System Verilog for the next gen of AMD Server SoCs.


Responsibilities include:

Working closely with the DFT Architecture and the various IP Design teams to align on the DFT requirements and successfully implementing the DFT RTL at the SoC level

Working closely with the ATPG team for coverage support, with the DV team on helping debugging and root-causing the test failures and with the PD team on DFT timing closure.



Experience in DFT architecture for complex chips

Experience in RTL development using Verilog/System Verilog having worked on RTL for IP and SoC integration

Proficient in doing basic unit-level verification using simulations.

Experience with RTL quality check tools/methodologies such as Spyglass, CDC, Lint is required.

Must have experience with integration of various IPs into complex SOCs.

Exposure to Static timing analysis & Timing closure is required.

Any prior experience with microprocessor designs is a plus.

Excellent hands-on debug skills and scripting skills are critical.

Must have good communication skills and the ability to work in a worldwide team environment.

Knowledge & experience of low power concepts, clock gating, power gating is a plus

Experience with post-silicon bring up is a plus



B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering

5+  years experience in RTL design



Requisition Number: 173046 
Country/Region/Location: India State/Province: Karnataka City: Bangalore 
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