STA Lead

Location: Bangalore, Karnataka, IN

Company: Advanced Micro Devices

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What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.


The AMD Radeon Technology Group (RTG) develops GPU ASIC design that enhances our daily lives as we are entering an age of immersive computing.  The RTG hardware engineering teams are distributed across Canada, US, China and India.  The team in India is engaging on the enthusiast and high performance GPUs.  




AMD is looking for an MTS Silicon Design Engineer to be part of a world class SOC design team and lead the work for


  • Full chip and block level timing closure for various stages of the entire design process (RTL, Synthesis, Place and Route and STA Signoff) .
  • Enhance and maintain all STA flows and methodology for multiple designs and across different technologies.
  • Work on all aspects of timing closure including Design rule checks , constraint validation , Noise analysis etc.
  • Work with various IP owners in developing and refining STA constraints for both full chip and block level.




  • 7-11 years of experience
  • Extensive experience in Primetime and extraction tools are an absolute must
  • Proficient in constraint generation and validation
  • Understanding/Experience in Complete ASIC flow (  RTL/Netlist to GDS )  with low power, performance and area optimization techniques
  • Understanding/Experience in Clock Tree Implementation Techniques for High Speed Design Implementation are required
  • Exposure to Constraint management tool and understanding of Verilog
  • Experience of multiple power domain implementation with complex UPF/CPF definition
  • Experience with CPU/GPU micro-architecture and their critical path
  • Excellent scripting skills (Perl/Tcl, Python, C++ ) 




  • Strong self-driving ability
  • Should have excellent communication skills (both written and oral)
  • Strong problem-solving skills



  • Qualification: Bachelors or Masters in Electronics /Electronics Engineering



Requisition Number: 110022 
Country/Region/Location: India State/Province: Karnataka City: Bangalore 
Job Function: 

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