Senior DFT Design & Verification Engineer

Location: Bangalore, IN

Company: Advanced Micro Devices

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What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

 

We are currently looking for DFT verification engineer. This is an exciting time at AMD and you will join DFX DV BGL Team and responsible for driving high quality DFT feature verification and ATE bring-up support.

 

What will you do in this role?

• Develop and execute pre-silicon verification test plans for DFT features of the chip. Develop directed and random verification tests to validate the functionality.

• Verify DFT design blocks and subsystems (such as MBIST, high speed IO PHY, fuse, clocks, reset) using complex SV/UVM or C++ verification environments. Construct SystemVerilog and/or C/C++ models and test sequence libraries for simulation.

• Build test bench components including agents, monitors, scoreboards for DUT. Compose tests, assertions, checkers, validation vectors and coverage bins to ensure verification completeness.

• Debug regression test failures to expose specification and implementation issues. Identify and address areas of concern to meet design quality objectives.

• Co-work with Front End and PD for synthesis optimization and smooth timing signoff.

• Develop high coverage and cost effective test patterns, and take part in ATE bring-up.

• Post silicon ATE and System level debug support of the test patterns delivered. Optimize the test patterns to improve the test quality and reduce test costs.

 

What experience and knowledge should you have?

Good understanding of standard DFT features including JTAG, MBIST, SCAN, fuse, IO-PHY loopback testing OR strong background in SystemVerilog (SV), SVA,  UVM verification methodologies and C++

• Strong debug skills and experience with debug tools such as Verdi.

• Knowledge of STA Constraints for various DFT modes.

• Experience with Verilog and/or System Verilog

• Experience with EDA simulation tools like Synopsys VCS, Cadence NCSIM, Verdi

• Experience with scripting languages like Tcl/Perl/Ruby/Python

• Working knowledge of Unix/Linux OS, file version control.

 

Additional skills:

• Experience in DFT specific verification and silicon debug is a strong positive.

• Experience in ATE debug, Synthesis, formal/LEC, or power analysis will be a plus.

• Strong analytical/problem solving skills and pronounced attention to details

• Excellent written and verbal communication

 

What educational background should you have?

• Minimum Bachelor Degree in Electronics/Electrical/Computer Science Engineering with 4 years of experience in relevant domain.

 



Requisition Number: 74146 
Country: India State: Karnataka City: Bangalore 
Job Function: Design 

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