MTS Silicon Design Engineer

Location: Beijing, Beijing, CN

Company: Advanced Micro Devices

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What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.


 Physical Design (power optimization)



Power is a more and more hot topic in IC design. We are a power/performance/area optimization methodology team.  In this position, you will work with global team especially physical design team for GPU chips physical design power optimization/reduction. Focus on physical design methodology optimization/update to improve chip Power and Performance/Area (PPA), including  RTL -> Syn ->place&route iteration/optimizing. The individual is expected to be an expert in physical design areas, it is a plus to have strong ability in multiple aspects in Front-End or RTL coding experience or Synthesis. The individual is expected know back-end power optimization very well, be very familiar with physical design power reduction methodology, not limited to PD but also can be Frond-end power reduction method. 



Strong self-motivation for technical topics, quick and deep learner, strong communication skill within global engineering team, strong team spirit help and support team members.



  • Develop state-of-art physical design power optimization methodology
  • Verify and test the power optimization methodology in physical design flow.
  • Closely co-work with GPU chip project design team, help/support/drive them adopt the power optimization methodology



  • Preferred 8+ years or more years of experience in physical design in digital ASIC chips
  • Be very familiar with physical design power optimization methodology, (eg. Clock-gating, power-gating, activity aware PnR, power friendly floorplan, DVFS, multibit re-banking de-bandking, scan path power …)
  • Expert in Back-End (physical design) EDA tools, especially the power calculation/optimization tools,
  • strong flow develop and custom script develop ability
  • Knowledgeable in all aspects of deep submicron ASIC design flow
  • Successfully gone through several complete product development cycles
  • work well with cross-functional teams
  • Good listening, writing and speaking English
  • Good communication skills, strong interpersonal skills and the flexibility



  • preferred MSEE with 8+ years or Bachelor with 10+ years of industrial experience in ASIC design



  • Beijing


AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability or any other characteristic protected by law. EOE/MFDV


Requisition Number: 112102 
Country/Region/Location: China State/Province: Beijing City: Beijing 
Job Function: 

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