SMTS Silicon Design Engineer

Location: Beijing, Beijing, CN

Company: Advanced Micro Devices

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What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.


SOC Design and Verification Engineer

It is a must that the candidate has one or more of the following experience/knowledge, such as GPU/ARM architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.


The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, driving execution of quality and timely result, capability to solve complex, novel and no-recurring problems and decision-making on critical technical areas.


• Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for GPU
• Provide the technical leadership to the DV team for the new GPU project
• Work independently on various DV tasks and providing technical guidance to the DV team.
• Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup


• Master in Electrical Engineering, Computer Science or related
• Good understanding on ASIC design verification flow
• RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences
• Knowledge on Perl, OVL, SVA, SV, UVM, OVM, script programming etc.
• GPU or large SOC verification experiences is a plus


• MSEE with minimum of 5 years, or BSEE with minimum of 7 years experiences in digital ASIC/SOC design verification


• Shanghai


AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability or any other characteristic protected by law. EOE/MFDV



Requisition Number: 111483 
Country/Region/Location: China State/Province: Beijing City: Beijing 
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