ASIC IP RTL Design Engineer - 92821

Location: Boxborough, Massachusetts, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

ASIC IP RTL Design Engineer - 92821


As a member of the Semi-Custom Business Unit within AMD, your execution will help bring to life customers' special requirements for designs to be used in a broad range of products, from tablets to gaming consoles to servers and more!  


The Role:

As a member of our IP RTL design team, you will take an active role in the lifecycle of digital IP development, resulting in a quality delivery of the IP RTL subsystem to AMD SOCs.  You'll join a tight-knit group that uses top notch tools in leading edge process technologies.  Collaborate with the architecture, SOC design, DFT, verification, and physical design teams for first pass silicon success!


The Person:

  • Excellent problem solving, analytical, and debug skills
  • A self-starter and able to independently drive tasks to completion
  • Strong verbal and written communication skills to work with team members across multiple sites


 Key Responsibilities:

  • Design of RTL blocks in verilog, which encompasses integration of 3rd party IP as well as custom logic design
  • Contribute to the specification and quality checks (lint, CDC, and power rule checks) of power-gated digital designs
  • Work collaboratively with other members of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC
  • Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up


Preferred Experience:

  • Understanding of processor and data fabric architectures
  • Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs
  • 3rd party IP integration
  • Power saving techniques, including clock gating and UPF-based power gating
  • Detailed understanding of ASIC design flows
  • Verilog lint tools (Spyglass) and verilog simulation tools (VCS)
  • Clock domain crossing (CDC) tools (0-in)
  • Power domain checking tools (VC_LP)
  • Strong Unix scripting and utilities (Shell, Perl, TCL, XML, Ruby, makefiles) for analysis and automation
  • Background in other aspects of ASIC implementation, such as Synopsys synthesis, timing constraints, PrimeTime static timing analysis, or verification is a plus 
  • Background in clocking, reset, power-up sequences and power management is a plus


Academic Credentials:

  • Bachelor or Master of Science Degree in Electrical or Computer Engineering
  • Prior experience with ASIC or IP design (outside of university) preferred



Boxborough, MA



Requisition Number: 92821 
Country: United States State: Massachusetts City: Boxborough 
Job Function: Design


AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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