CPU Core Verification Engineer -118085

Location: Boxborough, Massachusetts, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

 

CPU Core Verification Engineer

 

The Role:

Perform functional feature verification of high speed Microprocessor designs, including development of infrastructure, directed and random test suites at behavioral RTL level across SoC, Core and block hierarchies.

Develop environments, infrastructure and test plans to accommodate both full chip and stand alone block level verification and debug capabilities using simulation tools, debug tools and programming skills, based on in-depth understanding of the architecture and HDL/logical design of the microprocessor.

Develop an automated regression infrastructure setup for functional verification of high speed microprocessor designs. Based on detailed design architecture, develop, run and debug x86 assembly based directed tests and random exercisers to validate functionality and testability operation of the microprocessor design demonstrating C/C++/Perl/assembly programming, logic design and simulation skills. Resolve all simulation discrepancies and assertion responses for both behavioral and gate level logic models. Measure and analyze coverage results and take vital actions to fill in coverage holes.

 

The Person:

Candidate requires good communication skills and the ability to work with a team with varied strengths.

 

Preferred Experience:

Requires understanding or technical expertise in functional verification of microprocessor designs. Experience with Verilog/SystemVerilog HDL, programming in Perl, C/C++, logic simulation is a requirement. Direct experience with Verilog simulators is a plus. Requires very strong understanding of computer architecture and assembly programming.

 

Academic Credentials:

MS or PhD with some industry co-op experience desired (all degrees are related to CS or EE).

 

Location:

US, MA, Boxborough

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability or any other characteristic protected by law. EOE/MFDV

 

AMD employees who will be working onsite at an AMD US facility, are encouraged to provide proof of being fully vaccinated against COVID-19 upon their start date. This is for the safety of our employees, and to permit AMD to be prepared in the event the stay on Executive Order 14042: Ensuring Adequate COVID Safety Protocols for Federal Contractors is lifted. AMD is not requiring exemption / accommodation submittals at this time.

 

#LI-CS1



Requisition Number: 118085 
Country: United States State: Massachusetts City: Boxborough 
Job Function: Design
  

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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