Lead Memory PHY RTL Engineer- 94102

Location: Boxborough, Massachusetts, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

Lead Memory PHY RTL Engineer

The Role:

The Memory IO team is looking for a hardworking and experienced Design Engineering Lead for RTL and Firmware development of high-speed LPDDR, DDR and inter-chip IO IPs. Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP. This opportunity includes creation of new IO designs (microarchitecture, design, team leadership) as well as working on multiple designs and improving methodologies in parallel.

Be a part of a team that delivers Industry leading IP and help our specialists in RTL, FW, circuit and architecture teams develop leading edge and differentiating IPs.

The Person:

The candidate we are seeking will have strong analytical/problem-solving skills and pronounced attention to details. They must be a self-starter and able to independently drive tasks to completion. In addition, they will have strong interpersonal and communication skills.

Key Responsibilities:

  • Lead a team of RTL designers for memory I/O
  • Micro-architecture of digital blocks for memory IO, hardware/firmware partitioning.
  • Digital design and RTL coding
  • Direction and supervision of other RTL and firmware designers
  • Definition and optimization of training hardware and algorithms including optimization in silicon
  • Working with internal customers to define functional boundaries and specs

Preferred Experience:

  • Digital design engineering experience with successful tape-outs and technical leadership
  • Excellent knowledge of Verilog, C, C++ and a scripting language; experience with Python, Perl and TCL is a plus
  • Knowledge of clocking architectures, synchronization, and CDC methodology
  • SERDES, DDR, Memory Controller, or MAC Design experience is preferred
  • Strong understanding of computer organization/architecture.
  • Firmware Development experience is a plus
  • Mixed signal RTL experience is a plus
  • Experience with low level, physical phenomena oriented logic design is an asset (dealing with IO, clocking, voltage control, etc.)
  • Laboratory experience, including the use of equipment: oscilloscopes, logic analyzers, etc.

Academic Credentials:

Bachelor's degree in Electrical or Computer engineering is required. Master's or PhD degree is a plus.

Location:

Santa Clara CA, Boxborough MA, Austin TX, Markham ON

#LI-NB1

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability, or any other characteristic protected by law. EOE/MFDV
 



Requisition Number: 94102 
Country: United States State: Massachusetts City: Boxborough 
Job Function: Design
  

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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