Macro Modeling DDR Engineer

Location: Santa Clara, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

Macro Modeling DDR Engineer



We are searching for a senior RTL engineer to join the Memory PHY digital design team.  This is an exciting opportunity to be a member of the Memory IO design team responsible for defining, specifying, and implementing RTL for complex high speed circuit using System Verilog for the next generation of high-speed LP and DDR for AMD’s products.



The successful candidate will possess:

  • Excellent analytical and problem-solving skills along with attention to details
  • Must be a self-starter, able to drive tasks independently and efficiently to completion
  • Strong/effective communication skills
  • Enthusiastic team-first mentality
  • Ability to provide mentorship and guidance to junior engineers
  • Relevant academic background (M. degree preferred) and at least 8 years’ progressive experience



  • Drive a modeling plan with support from circuit design team and architecture team
  • Technical expert for a macro modeling team
  • Develop Verilog/System Verilog RTL for macro models
  • Analyze complex digital design problems and propose solutions
  • Mentor and provide technical leadership to junior digital and mix signal designers within the team
  • Work with Design Verification team to ensure functional correctness
  • Work with circuit design team on various quality metrics associated with circuits models



  • Solid understanding of mixed signal design component
  • Proven experience in digital design from specification to successful silicon
  • Experience in mixed signal high speed control system around DDR and/or GDDR/HBM, high speed SERDES is  a plus.
  • Experience in designs with multiple power domains
  • Experience in designs with multiple clock domains
  • Experience in industry standard ASIC CAD tools such as logical equivalency, lint, CDC, RDC, etc.
  • Experience in advanced semiconductor technologies, preferably FinFET
  • At least 8+ years’ progressive experience in RTL Design



  • Relevant academic background (Master’s degree preferred)

Location: Santa Clara CA, Boxborough MA, Austin TX, Markham ON


Requisition Number: 94102 
Country: United States State: California City: Santa Clara 
Job Function: Design


AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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