SERDES System Level Design Engineer

Location: Santa Clara, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

Title: SERDES System Level Design Engineer

 

The Role : The candidate will be a member of the high speed SerDes design team supporting the definition, specification, system simulation and implementation of future SerDes IPs in the 32Gbps+ range, especially in the System Modulation scheme area. The focus of the activity will be centered around the micro-architecture for the critical high-speed analog and digital blocks, definition of specifications for the high speed data path; definition of algorithms for calibration, adaptation, equalization, clock and data recovery; and development of abstracted models for link performance simulations.

 

 

The Person : 

  • Will have analytical thinking and inventive spirit in combination with a solid understanding of risks and risk mitigation
  • Strong/effective communication skills
  • Enthusiastic team-first mentality

 

Responsibilities :

 

  • Contribute to the definition of microarchitecture and to the design implementation of various state-of-the-art, high-speed (32-64Gbps) blocks for SerDes PHYs, especially in the PAM4 area
  • Develop models for link-level statistical performance simulation of the PHY (Bit Error Rate, eye-opening) and application of the same to the development and optimization of design.
  • Documentation of the micro-architecture and algorithms, and guidance of Analog, Digital, Firmware and Verification teams on the implementation/verification of the same 
  • Work closely with various disciplines, especially Analog Mixed Signal design, Digital Design and Firmware, as well as Design Verification to ensure optimal implementation of the overall PHY architecture and algorithms and full coverage of the features
  • Participate and contribute to the definition of development flows that improve efficiency and quality of execution 

 

 

 

Preferred Skilled Sets :

 

  • A proven successful track record in micro-architecture and modeling for SERDES
  • Solid and hands-on knowledge of algorithms and adaptation/calibration/ clock and data recovery techniques for high-speed SERDES, especially in the area of PAM4
  • Solid knowledge of industry-standard tools and best-in-class practices for PHY modeling, both in terms of abstracted models (e.g. Matlab/Simulink) as well as Verilog-based.
  • Good knowledge in high-speed SerDes design (signaling/equalization techniques, analog/mixed-signal circuit design, and signal integrity).
  • Ability to dig into circuits and RTL or FW code to understand the detailed implementation

 

Education Requirements

  • Masters or PHD in Electrical or Computer Engineering

 

*LI-AP1



Requisition Number: 78250 
Country: United States State: California City: Santa Clara 
Job Function: Design
  

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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