Sr. Functional Design Verification Engineer - 75390

Location: Boxborough, Massachusetts, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

As a Senior Functional Verification Engineer for the Core Unified Memory Controller (UMC) IP group, you will 

  •      Provide technical expertise for developing the functional verification strategy of AMD’s next generation Unified Memory Controller (also known as Dram Controller IP);  
  •      Understand the architecture of the Dram Controller IP and create the Stimulus, checkers and coverage for the functional block being designed
  •      Maintain and enhance existing verification infrastructure
  •      Develop new test plans, functional coverage points, and test bench components like test-cases, monitors, scoreboards, sequencers, and sequences
  •      AMD uses IP-XACT methodology.
  •      UMC integrates a third party ddrphy into our IP and integrate the UMC IP tag into server and client SOCs.

 

What makes this an interesting opportunity? As a functional verification engineer, you will be

·         Looking at the RTL to find functional bugs,

·         Working with the RTL team to fix the bugs,

·         Reading the AMD Memory Controller MAS (micro-architectural Spec) and Jedec DRAM Guidelines (ddr4/lpddr4/lpddr5//ddr5/NVDIMM-p(ddr4 and ddr5)) and DFI (Dram Phy Interface Spec)

·         Developing test plans, functional coverage points, monitors, scoreboards, sequencers, and sequences, which utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved.

 

Why is this job exciting? Your daily responsibilities will comprise of a mixture of:

  •     Ownership of a piece of our test bench,
  •     Verification Expert on an area of dram/ddrphy or dram controller sub-block
  •      Planning & execution of feature additions and
  •      Bug fixes
  •      Debug of regression signatures.
  •      Closing Functional Coverage to zero holes on each Client and Server Variant in area assigned;
  •      Innovating UMC testbench:  Improving UMC IP testbench each year (build times, re-use, integration times/flow, automating flows, etc.) 

 

The Person

What skills, experience and qualifications do I need?

  • You will have demonstrated technical expertise in functional verification of complex designs including test planning, test bench development, stimulus generation, checking, and functional coverage.
  • Possess strong OOP and debug skills.
  • You have significant experience with Verilog and System Verilog, C++, Perl, and logic simulation.
  • You have experience with UVM.
  • Excellent communication & Analytical thinking skills
  • You can work independently as well as in a cross-site team environment.
  • You are knowledgeable of entire design process from Design specification, defining architecture, micro-architecture, RTL design and functional verification, Tape-out, and post-Si debug.
  • Experience with dram controllers, memory models (ddr4, lpddr4, ddr5, lpddr5, hbm), Jedec and/or ddrphy(s) is a plus.
  • You bring hands-on experience in Design/Integration activities.
  • Some exposure to DFT is a plus.
  • You can work closely with RTL Designers and SOC Design teams across multiple sites.

 

EDUCATION:

  • Master’s in Computer Engineering with at least 2 years of Functional Verification Experience in ASIC design;
    • or Bachelor’s in Computer Engineering with at least 6 years working Verification of ASIC design (preferably IP Functional Verification)
    • Would accept Electrical Engineering degree if concentration in Computer Architecture or microprocessor design

 

#LI-SC2



Requisition Number: 75390 
Country: United States State: Massachusetts City: Boxborough 
Job Function: [[customString7]] 

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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