Timing Analysis Lead Engineer - 97043

Location: Portland, Oregon, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

Timing Analysis Lead Engineer

 

The Person:

Will have strong analytical/problem-solving skills and pronounced attention to details. Must be a self-starter, and able to independently drive tasks to completion. Will have strong interpersonal and communication skills

 

The Role:

 The Memory IO team is looking for an experienced Implementation and Timing Analysis Lead for development of high-speed LPDDR,DDR and inter-chip IO IPs.  Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP.  This opportunity includes working on from scratch high speed PHY designs as well as enhancing design methodologies.

 

Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, Circuit and architecture teams develop leading edge and differentiating IPs.  

 

 RESPONSIBILITIES:

  •  Internal Timing Closure of high speed (10G+) / mixed signal circuits
  • Interface timing / Characterization of macro blocks
  • Digital Implementation and Timing closure of high speed digital designs
  • Timing Feedback and Block partitioning feedback to RTL and Circuit designers
  • Working closely with mixed signal, physical design and layout teams to achieve timing closure.

 

Preference & Skill Sets :

  •  Digital design engineering experience with successful tape-outs and technical leadership
  • Experience with transistor level custom logic design.
  • Experience with transistor and gate-level static timing and noise analysis
  • Experience with writing and verifying timing constraints
  • Experience with Nanotime, Primetime, and other timing analysis tools.
  • RTL experience is a plus
  • Mixed signal design experience is a plus
  • Experience with low level, physical phenomena-oriented logic design is an asset (dealing with IO, clocking, voltage control, etc.)

 

EDUCATION:

  • Bachelor's degree in Electrical or Computer engineering is required. Master's or PhD degree is a plus.

 

Location :

  • Santa Clara CA, Boxborough MA, Austin TX, Markham ON

 

#LI-DC1


AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability, or any other characteristic protected by law. EOE/MFDV
 



Requisition Number: 97043 
Country: United States State: Oregon City: Portland 
Job Function: Design
  

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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