Cache/Memory Subsystem Verification Lead - 179661

What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

Cache/Memory Subsystem Verification Lead 

Role:

The Cache and Memory team is looking for sharp and motivated Lead Design Verification Engineer who are interested in verification of Graphics products. You will work and learn some of the industry’s cutting edge micro architectural designs and be responsible for leading the verification of the sub-system.

Person

The candidate we are looking for is a keen learner and ready to take on tasks that contribute towards efficient design verification and improve the quality of the products. The ideal candidate is continuously thinking of ways to improve efficiency and performance.

Responsibilities:

• Verification Lead for various cache and buffer blocks
• Verify sophisticated design blocks in  complex SV/UVM  and C++ verification environments
• Develop and execute pre-silicon verification test plans
• Develop directed and random verification tests to validate block and IP functionality
• Develop verification components and tools
• Develop verification functional coverage using industry standard coverage analysis tools/methods
• Debug regression fails
• Replicate functional issues found in external environments or post-silicon; review, improve tests to verify bug fixes

Preferred skills:

• Requires very strong understanding of computer architecture.
• Experience with System Verilog and UVM.
• Experience with C++, Verilog, Perl, and debugging with Verdi
• Proven technical expertise in functional verification.
• Strong communication skills and the ability to work independently as well as in a cross-site team environment.

Academic credentials:

• Bachelors or master’s in electrical/electronic engineering.

Location:  Santa Clara, CA

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Requisition Number: 179661 
Country: United States State: California City: Santa Clara 
Job Function: Design  

Benefits offered are described here.

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