Display IP Verification Infrastructure and Methodology Engineer-146641

Location: Cambridge, Cambridgeshire, GB

Company: Advanced Micro Devices

Apply now

Apply for Job

What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.



Senior Design Verification Infrastructure and Methodology Engineer

The Role:

The Display IP is one of the foundational IP's within AMD and is incorporated in all AMD SOC's which feature direct connectivity to a display device through Display Port, HDMI or USB-C connectors.  Beyond the output encoding, the Display IP design is responsible for the pixel processing, memory real time performacne and system power reduction functionality within the SOC.

The Display Controller team within the Radeon Technologies Group(RTG) is looking for an experienced design verification professional to take on the role of DV methodology, infrastructure and automation within the Display IP organization. She/He will be part of a team responsible for developing a scalable DV flow with emphasis on automation, architecture, power and performance.  The qualified candidate will work closely with multiple teams and groups on charting verification strategy, automating the verification flow, defining the test bench architecture and evaluating/deploying new DV methodologies and solutions with the goal of enabling the scalable IP DV strategy and infrastructure needed to support AMD’s aggressive product roadmap.


The Person:

  • Creative and innovative thinker who loves technical problems.
  • Organized, enthusiastic and self-motivated with a strong interest in verification methodologies and automation.
  • Be a self-starter, pro-active, and take ownership to drive tasks to completion.
  • Excellent communication skills (verbal and written) with strong problem-solving, and attention to detail.
  • Ability to work in a multi-discipline team and global setting as a solution enabler.


Key Responsibilities:

  • Work with system/DV architects on defining various aspects of the overall IP verification strategy and methodology.
  • Develop and maintain different types of automation flows and corresponding infrastructure.
  • Develop or enhance in-house tools for productivity enhancement, metric collection, and tracking.
  • Oversee and enhance test regression system and website
  • Identify performance and productivity bottlenecks and come up with innovative solutions.
  • Drive technical initiatives to improve AMD’s capabilities in IP validation/verification, including tool and script development, technical and procedural methodology improvement, and various other internal and cross-functional technical initiatives.
  • Architect and hands-on development of testbench components as well as developing test and sequence libraries, by applying Objected Oriented Programming Verification techniques following UVM methodology.
  • Evaluate and deploy the latest verification solutions, tools and methodologies.
  • Own and execute on verification of a sizable design by applying UVM verification methodology
  • Compose test and coverage plan, test sequence and and validation vectors to ensure functional completeness
  • Build test bench, agents, monitors, models and scoreboard for DUV
  • Debug functional/performance bugs in Display IP


Preferred Experience:

  • Proven  experience in the ASIC industry including a design verification lead or DV architecture role
  • Deep knowledge of DV infrastructure, Make flow and other automation flows, shell, perl, python, ruby.
  • Experience in flow tools (e.g., dj, Node.js, Vue.js), disctributed computing (LSF), and database (e.g., SQL) is a plus
  • Proficiency in Verilog, SystemVerilog, and C/C++
  • Extensive experience verifying complex designs using UVM, OVM or rquivalent
  • Expertise in constrained random verification methodologies, metric/coverage driven verification and formal verification
  • Must have ASIC design verification experience in test plans, test creation and triage, coverage and assertion
  • Exposure to emulation/HW acceleration for design verification, architectural prototyping, and virtual platforms for SW enablement is an asset
  • Must demonstrate strong analytical thinking and problem-solving skills with excellent attention to detail
  • Must have good teamwork and interpersonal skills 


Academic Credentials:

  •  BS degree in Electrical/Computer Engineering or Computer Science
  • #LI-DC3


Requisition Number: 146641 
Country: United Kingdom Province: Cambridgeshire City: Cambridge 
Job Function:Design


AMD is an inclusive employer dedicated to building a diverse workforce. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective provincial human rights codes throughout all stages of the recruitment and selection process. Any applicant who requires accommodation should contact AskHR@amd.com.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services.


Apply now

Apply for Job

Share this Job