Design Verification Engineer

Location: Austin, Texas, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

TITLE: Design Verification Engineer

 

THE ROLE:  

We are currently looking for ASIC Design Verification Engineer who will be involved in all aspects of IP verification starting from creating a verification strategy, defining test plans for upcoming features, identifying different performance scenarios. Driving decisions with other architects while a feature is defined and also making sure the feature is deployed in all relevant AMD products.

The IOMMU team (inside NBIO organization) is all about leading-edge I/O technologies. From developing high-speed next-generation PCIe and USB interconnects, to I/O virtualization technologies powering data center and machine learning workloads, these IPs touch all AMD products – CPUs, Graphics cards, and Game consoles. This team is part of the bleeding edge of development for tomorrow’s client, server, embedded, graphics, and semi-custom chips.

 

THE PERSON: 

  • Will demonstrate strong analytical thinking and problem-solving skills with an excellent attention to detail
  • Will have good communication and writing skills
  • Will have good teamwork and interpersonal skills

 

RESPONSIBILITIES:

  • Closely work with feature architects to come up with verification strategy and execution plans
  • Participate in verification of complex IP blocks, take end to end ownership of key features for all projects
  • Work on test plans, test case development, testbench enhancement, regression and coverage closure
  • Developing Testbenches and Verification Components such as UVCs, models, BFMs, and Re-usable Verification Environments
  • Writing, Modifying, and Maintaining Random and Directed Test Cases and Libraries in SystemVerilog/UVM/SystemC
  • Analyzing Functional, Code, and Test Plan Coverage
  • Implementing Assertions, Checkers, and Monitors
  • Deploying Industry-Leading Verification Methodologies such as UVM and Formal Verification
  • Triaging and Debugging Regressions
  • Reproducing Functional Bugs found in Silicon in Simulation and/or Formal Verification tools
  • Conducting and participating in Code Reviews

 

Preferred Experience & Skill sets:

  • Extensive hardware verification experience
  • Proficient in Verilog, System Verilog, C and C++, UVM, and working in Linux and Windows environments
  • ASIC design knowledge and be able to debug Verilog RTL code using simulation tools
  • Excellent programming skills
  • Demonstrate strong analytical thinking and problem-solving skills with an excellent attention to detail
  • Experience in security verification would be an asset

     

Education:

  • Bachelor's in EE ( Master's preferred ) 

 

#LI-SL1

 


Requisition Number: 148685 
Country: United States State: Texas City: Austin 
Job Function: Design
  

Benefits offered are described here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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