CPU Core RTL Design Engineer 2 (80107)

Location: Ft Collins, Colorado, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

CPU Core RTL Design Engineer

 

The Role:

This Design Engineer on the Cache Hierarchy Chip Pervasive Logic (CPL) team in Fort Collins, Colorado will contribute to the team using experience and gaining new experience with Clocking, Reset, Power and Power Domain RTL design.

 

The Person:

This engineer on the Cores team will ideally have the following experience and attributes:

  • Eagerness to learn and grow as a CPL design engineer.
  • Collaborate effectively towards the success of the project by working closely with logic design, physical design and verification teammates across the wider organization
  • Demonstrate a responsive track record of engaging with a diverse set of teams and across a broad set of technical areas to facilitate design delivery

 

Key Responsibilities:

  • Collaborate with a dedicated team of engineers to define and implement CPL microarchitecture for AMD CPUs.
  • Optimal deliver a design from concept through tapeout by innovating through complex and ambitious requirements.
  • Drive design closure gaining experience with Static Timing, CDC/Gate CDC, and Static Power analysis.
  • Identify customer challenges and insert a compelling AMD value proposition to address challenges.
  • Make technical contributions and innovations that enable high performance, high frequency, and power efficiency on caches, fabrics, and interfaces of our server, desktop, and laptop CPUs

 

Preferred Experience:

  • Proficiency with Verilog HDL, Clock/Power Domain Crossing concepts, and Power Management concepts.
  • Understanding of modern CPU architecture - prior experience designing shared cache or last level cache and related IPs a plus.
  • MS in EE/CE with relevant coursework and project experience, or BS in EE/CE with relevant coursework and project experience

 

Academic Credentials:

  • Master’s degree in Computer Science, Electrical and Computer Engineering, or Electrical Engineering. Masters are preferred/desirable.

 

Location:

Fort Collins, CO

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Requisition Number: 80107 
Country: United States State: Colorado City: Ft Collins 
Job Function: Design
  

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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