Silicon Design Engineer - NBIO IOMMU Verification Lead (110725)

Location: Hsinchu, Taiwan, TW

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

Silicon Design Engineer -NBIO IOMMU Verification Lead

 

THE ROLE:

AMD NBIO (North Bridge IO) team delivers industry leading high-performance interconnects IP for all AMD products including dGPU, APU, Server, Data center and Game consoles. NBIO global operates seamless from China, North America and Europe. IOHUB sits in the center of all data paths, it includes 2 sub IP name as IOHub Core and IOMMU.

The IOMMU (I/O Memory Management Unit) is a system function that translates addresses used in DMA transactions, protects memory from illegal access by I/O devices, and remaps peripheral interrupts. It plays a critical role on IO virtualization technology which is widely used in today’s mega-data center. We developed remote IOMMU and remote L1 technology to match project requirements. We’re seeking a candidate as remote IOMMU and remote L1 tech lead in HOHUB team.

 

THE PERSON:

Candidate will work as local remote IOMMU/L1 verification leader, co-work with local engineers and global IOHUB team on cutting edge remote IOMMU/L1 development. Candidate needs to have solid IP verification background and outstanding global communication skills. Someone who has tech lead experience with good Chinese and English communication skills should be basic qualified our requirement.

 

KEY RESPONSIBILITIES:

  • Remote IOMMU/L1 new feature effort scoping
  • Remote IOMMU/L1 feature test plan and DRVR writer, split down the tasks and assign to Engineers
  • Attend global conference call for verification strategy alignment, status sync up etc. with distributed team
  • Drive and monitor other specialists to accomplish tasks on schedule
  • Sign-off owned features/projects
  • Short term global travel if needed

 

PREFERRED EXPERIENCE:

  • Global company working experience, fluent oral English
  • Complex IP/ASIC/SOC Design Verification, direct experience in IP/SOC or Processor (CPU or GPU) or Industry bus standard (PCI-e, HT) is preferred.
  • Good knowledge of UVM/Verilog/System C/SystemVerilog.
  • Solid background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA), insights into random techniques.
  • Experience of verification lead is an asset.
  • Experience of verification planning is an asset.
  • Knowledge of Virtualization is an asset.
  • Strong scripting languages (Python, Perl, C Shell, Makefile, …) experience is plus.
  • Strong collaboration skill set
  •  

ACADEMIC CREDENTIALS:

MSEE or BSEE with experience in digital ASIC/SOC design verification

 

LOCATION:

Hsinchu, Taiwan

 

#LI-SC1



Requisition Number: 110725 
Job Function: Design  

 

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