MTS Silicon Design Engineer(7)

Location: Hyderabad, Telangana, IN

Company: Advanced Micro Devices

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What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

 

Requirements

Key Responsibilities:

• Responsible for participating in the pre-silicon verification for full chip, blocks, multi-chip and

system level verification

• Responsible for participating in the post-silicon ATE pattern debug

• Jtag, Bscan, BIST, High speed IO Loopback, PLL , Clock & Analog Observation verification

• Specifying design verification plan at soc level/IP level

• Specifying or reviewing verification plans for complex blocks within the ASIC

• Responsible for developing complex verification environment using the latest

coverage/assertions based verification design methodology, which includes :

o self-checking, reusable, automated verification environment : both at full-chip & block level

o Constrained random generators and reference models

 

Job Requirements and Skills:

• B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering

• Minimum 8+ years of experience in ASIC Design Verification

• Expertise on Design for Testability (DFT) features verification

• Must have excellent knowledge of ASIC Design Flow

• Experience in developing complex testbench/model in verilog, System verilog or SystemC

• Experience with coverage-based verification methodology

• Experience in writing testplans and testcases

• Excellent debug skills in both functional simulations are must.

• Experience in random test generation, coverage analysis, failure debug

• Strong Verilog, SystemVerilog, PLI interface, C/C++, Perl/shell scripts programming skills.

• Must have good communication skills and the ability and desire to foster a team environment.

EXP: 7-15 Years

Location: Hyderabad

We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.

 

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Requisition Number: 82017 
Country: India State: Telangana City: Hyderabad 
Job Function: 
Design  

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