Product Application Engineer 2

Location: Hyderabad, Telangana, IN

Company: Advanced Micro Devices

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What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

 

We are looking for a self-motivated engineer to work on RTL synthesis and implementation analysis, design tuning and timing closure for FPGAs. We are looking for smart, creative people who have a passion for solving complex problems.  

The ideal candidate should have a strong background in RTL design using Verilog/VHDL and exposure to timing closure with foundations in timing analysis & digital design. The candidate should have a solid understanding of timing constraints, RTL coding styles and applications. Daily duties include the following: 

  • Explore critical tool issues seen by internal IP teams or customers and help identify workarounds and future enhancements 

  • Tracking, prioritizing, and assigning reported tool issues to the appropriate engineering teams 

  • Adopt proper tool methodology, and illustrate best practices via examples, tutorials and demos 

  • Identify, document and present new design techniques leading to higher productivity or higher performance 

  • Staying current with and proposing the internal use of industry approaches, algorithms, and practices 

 

Qualifications - External

Required Education and Experience:   

  • BS or MS in EE or CE with 3+ years of experience in digital design and/or timing closure  

  • Strong background in RTL design using Verilog/VHDL  

  • Timing Constraints (SDC) & Static Timing Analysis  

  • Strong understanding and usage of ASIC and/or FPGA software toolchain  

  • Strong Digital Design Fundamentals and applications  

  • Scripting languages such as TCL, Perl or Python  

Preferred Experience: Exposure to any of these areas:   

  • Applications and Designs in Wireless/Wired domain 

 



Requisition Number: 153157 
Country/Region/Location: India State/Province: Telangana City: Hyderabad 
Job Function: 
Product Engineering  

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