MTS Silicon Design Engineer

What you do at AMD changes everything 

We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team.

AMD together we advance_

THE ROLE:

System Management Unit (SMU) IP is the backbone of AMD SOCs. We design and deliver cutting-edge technologies of network-on-chip (NoC), advanced power management, clocking, security processor and cryptography, etc. The SRDC SMU team is a critical part of global SMU team.

THE PERSON:

If you’re: self-motivated, passionate to push the boundary and explore new territory, believer of sharing and mutual influence, you’re exactly who we look for.

• Develop comprehensive block level verification testplan for DUT
• Develop testbench and testcases with SystemVerilog/UVM verification methodology
• Develop verification IP which can be reused at different levels of verification, including block, sub-system, SoC, etc
• Support sub-system and SOC level verification

PREFERRED EXPERIENCE:

• Excellent knowledge of design verification methodology, such as OVM/UVM, System Verilog
• Solid experiences with simulation model creation and the testbench build
• UPF/CPF based power-aware simulation experience is a plus
• C/C++ software development experiences is a plus
• Good communication skill and fluent English

ACADEMIC CREDENTIALS:

• Master or Bachelor degree in EE/CS is preferred

LOCATION:

Shanghai, China

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Requisition Number: 177429 
Country/Region/Location: China State/Province: Shanghai City: Shanghai 
Job Function: Design