MTS Silicon Design Engineer

What you do at AMD changes everything 

We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team.

AMD together we advance_

The candidate is preferred to be MSEE with minimum of 6 years, or BSEE with minimum of 8 years experience in digital ASIC/SOC design verification.  

The candidate must have:

1. Deep understanding on ASIC/SOC design flow
2. Strong coding with Verilog and SystemVerilog
3. Good knowledge of design verification methodology UVM.
4. Expert for scripting language, such as Perl, C shell, Makefile, Ruby.
5. Many experiences with sequence creation, functional cover groups and assertion coding.
6. Many experiences with simulation model creation and the testbench build
7. Strong C/C++ software development experiences

It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, PCI-E/PCI bus, UFS Flash host controller,  low power design, clock generation and control,  Ethernet, JTAG, etc.

The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, , driving execution of quality and timely result, capability  to solve complex, novel and no-recurring problems and decision-making on critical technical areas

Responsibility:

The successful candidate will work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market. The candidate will provide the technical leadership to the DV team for the DV infra tasks. Including DV flow setup cross IPs.  DV enviroment/testbench setup.  New DV methdology adoption.  

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Requisition Number: 178803 
Country/Region/Location: China State/Province: Shanghai City: Shanghai 
Job Function: Design