Silicon RTL Design Manager

Location: Markham, Ontario, CA

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

 

 

Silicon RTL Design Manager

The role:

An RTL Design Manager role in our System Management Unit (SMU) IP team, where a large number of individual embedded micro-processor (MP) subsystems and associated hardware accelerators, vital to improve subsystems performance and functionality, are designed and verified. These subsystem IPs provide high performance functions to System on Chip (SoC) products across all AMD business units such as client computers, servers, discrete graphics, and gaming. As a hands-on design manager, you will lead a team of RTL design engineers and work on block level RTL design and subsystem level integration for a variety of embedded MP subsystems. Your expertise will impact security policy management, cryptography, data compression, high throughput DMA, power management, and many other subsystem applications.

The person:

An experienced hardware RTL design leader with strong records of technical leadership and hands-on execution to meet block level IP and MP subsystems design and verification project milestones. A technical mentor and forward-thinking leader who demonstrated strong capability in establishing advanced design methodology and workflow, anticipating/analyzing/resolving technical and planning issues, and enjoyed interacting with team members. A strong written and verbal communicator with strong problem solving and attention to detail skills along with professional interpersonal communication capability.

Key responsibilities:

  • Develop block level RTL IP and MP subsystems feature spec, hardware micro-architecture, synthesizable RTL design methodology, and automated design infrastructure
  • Lead development and debugging of RTL designs using C-DPI directed test methodology, and/or using verification team’s testbenches and tests, and achieve design feature closure (feature spec vs. coverage metrics)
  • Manage regression result triaging, hardware debugging, and coverage analysis, and resolve technical issues with design, verification, and other teams, to achieve design feature and design rule closures (i.e. linting, timing, DFT, DFP and other rules)
  • Participate in verification testbench and test plan specification, influence testbench architecture development (design for verification aspect), review and improve feature and coverage test plans
  • Coordinate resolution of IP integration issues with SoC Integration, SoC DV and post-silicon validation teams
  • Collaborate with project management and other team leads on RTL design delivery against the project milestone requirements and design quality metrics
  • Collaborate with other technical leads on process, methodology, and technical enhancements to RTL design, to drive continuous improvement and positive changes

Preferred experience:

  • Proven experience in designing commercially successful IP and subsystems
  • Demonstrated understanding of CPU and MP subsystem architecture, datapath hardware accelerator micro-architecture, as well as FPGA based simulation or emulation methodology
  • Proficient in Verilog, System Verilog (an extra asset), and scripting (using Tcl, Ruby, Perl, Python and Makefile)
  • Deep knowledge about state-of-art RTL design and verification methodology and best practices such as C-DPI
  • Excellent understanding of standard bus/interface protocols (i.e. AXI, AHB, AMBA)
  • Excellent experience with ASIC design tools: synthesis, linting, simulation, debugging, power aware simulation, etc.
  • Strong ability to provide mentorship and guidance to junior and senior engineers, a very effective team player, a positive influencer on team morale and culture
  • Prior technical management experience is a plus asset

Academic credentials:

  • Major in Electrical Engineering, Computer Engineering, or Computer Science, or possibly a related field
  • Master's or PhD Degree preferred

Location: 

Markham, Ontario

 

 

 

AMD is an inclusive employer dedicated to building a diverse workforce. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective provincial human rights codes throughout all stages of the recruitment and selection process. Any applicant who requires accommodation should contact AskHR@amd.com.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services.

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