Formal Design Verification Engineer- 93761

Location: Munich, Bavaria, DE

Company: Advanced Micro Devices

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What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.


Title : Formal Verification Engineer

The Role : This position is for a design verification engineer. The successful candidate will use formal verification technologies to complete functional verification of state-of-art design. Formal technologies include Formal Property Verification (FPV), Sequential Equivalence Check (SEC/SEQ/SLEC), Connectivity Check (CC).

The Person : Will enjoy learning, growing and working in a fast paced environment

Responsiblities :

  • Crafting verification plan
  • Writing formal properties
  • Running formal verification tools
  • Debugging failures
  • Discussing issues with designers
  • Document, report and issue tracking

Preferred skillset & Experience:

  • A property language like SystemVerilog Assertion (SVA)
  • Understanding a HDL language like Verilog or VHDL
  • Concept and flow of design verification
  • Previous FPV experience or eager to learn

Education : Electrical or Computer Engineering

Location : Germany



Requisition Number: 93761 
Country/Region/Location: Germany State/Province: Bavaria City: Munich 
Job Function: 

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