Lead Memory PHY RTL Engineer Engineer - 88941

Location: Munich, Bavaria, DE

Company: Advanced Micro Devices

Apply now

Apply for Job


What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

 

Lead Memory PHY RTL Engineer

 

The Person:

Will have strong analytical/problem-solving skills and pronounced attention to details. Must be a self-starter, and able to independently drive tasks to completion. Will have strong interpersonal and communication skills

 

The Role:

 

The Memory IO team is looking for a passionate and experienced Design Engineering Lead for RTL and Firmware development of high-speed LPDDR,DDR and inter-chip IO IPs.  Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP.  This opportunity includes creation of new IO designs (microarchitecture, design, team leadership) as well as working on multiple designs and enhancing methodologies in parallel.

 

Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit and architecture teams develop leading edge and differentiating IPs.  

 

 

RESPONSIBILITIES:

 

  • Lead a team of RTL designers for memory I/O 
  • Micro-architecture of digital blocks for memory IO, hardware/firmware partitioning.
  • Digital design and RTL coding
  • Direction and supervision of other RTL and firmware designers
  • Definition and optimization of training hardware and algorithms including optimization in silicon
  • Working with internal customers to define functional boundaries and specs

 

Preference & Skill Sets :

 

  • Digital design engineering experience with successful tape-outs and technical leadership
  • Excellent knowledge of Verilog, C, C++ and a scripting language; experience with Python, Perl and TCL is a plus
  • Knowledge of clocking architectures, synchronization, and CDC methodology
  • SERDES, DDR, Memory Controller, or MAC Design experience is preferred
  • Strong understanding of computer organization/architecture.
  • Firmware Development experience is a plus
  • Mixed signal RTL experience is a plus
  • Experience with low level, physical phenomena oriented logic design is an asset (dealing with IO, clocking, voltage control, etc.)
  • Laboratory experience, including the use of equipment: oscilloscopes, logic analyzers, etc.

 

EDUCATION:

  • Bachelor's degree in Electrical or Computer engineering is required. Master's or PhD degree is a plus.

*LI-AP1



Requisition Number: 88941 
Country: Germany State: Bavaria City: Munich 
Job Function: 
Design  

Apply now

Apply for Job

Share this Job