Sr. Silicon Design Engineer

Location: Roseville, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

Sr. Silicon Design Engineer

 

We, the Graphics Memory Hub (GMHUB) team, are responsible for developing highly optimized IP components for performance critical data fabric connectivity and virtual memory management. Our team is involved in most SOCs that are shipped by AMD, including console, discrete graphics, and low power SOC’s.

 

We use the latest bleeding-edge tools / methodology / design techniques to implement complex digital designs with a focus on optimizing performance, power, and area.

 

RESPONSIBILITIES:
[A] Responsible for Synthesis & Timing closure using industry-standard tools like Design Compiler and Prime Time
[B] Explore various Synthesis flow options to bridge the difference between Physical Design teams QoR with that of IP
[C] Independently be able to evaluate and map RTL to Netlists for coming up with possible timing improvements with RTL modification.
[D] Understanding and Debugging Logic Equivalency failures using Formality

[E] Evaluate all aspects of the process flow from high-level design to synthesis, timing, power and other Front End activities like Lint / CDC etc
[F] Should be able to come up with various simulation scenarios for power stress and perform Power Analysis using state of art EDA tools like Power Artist / Prime Time (Power)
[G] Should have strong scripting abilities, and familiarity with databases to automate wherever it is necessary

 

This is a very high visibility role, involving communication across various geographies. Should be able to communicate effectively and efficiently to support various stakeholders.


REQUIREMENTS:
[A] A strong interest and passion in ASIC Design is a MUST
[B] An inquisitive mind that is eager to explore beyond the defined processes and flows, for highest quality deliverables.
[C] Strong Digital logic Design principles and Analysis skills.
[D] Some experience with Simulation, Synthesis tools is good to have skill but NOT a MUST.
[E] Good understanding of Verilog HDL coding for synthesis and ASIC Frond-End implementation flows
[F] Strong UNIX and scripting languages like shell/Perl/Python
[G] Familiarity with Tcl is a huge plus.
[H] Strong problem solving , debugging skills, and attention to detail is a MUST.
[I] Self motivated team player with strong passion for achievement and career development with Never say die attitude

EDUCATION:
Minimum BS EE/CE, or equivalent degree with about ~2 years of hands-on design / synthesis / timing closure experience in ASIC product development.

New College Graduates with strong Digital Design skills are welcome to apply.

 

#LI-BS1



Requisition Number: 121622 
Country: United States State: California City: Roseville 
Job Function: Design
  

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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