MTS Design Verification Engineer - PCIE

Location: San Jose, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

Job Description

This is an exciting opportunity to work in the Xilinx SOC Verification Team as a Design Verification Engineer. The candidate will have an opportunity to work on state of the art verification environment using UVM verification methodology and C. Besides owning block level test bench, the candidate will have opportunity to work on sub system level verification and participate in silicon bring up.

 

We are specifically looking for candidates who have experience with verification of PCIE

 

 Responsibilities

  • Create block level verification plan, test plans and full chip test plan
  • Develop block level test bench and tests in UVM methodology including scoreboard
  • Work on subsystem level verification
  • Work with designers to get coverage closure
  • Port the block level tests to full chip test bench
  • Integrate VIPs as needed
  • Work with software, validation and emulation teams as needed.
  • Work on other aspects of verification like CDC, gate simulation.
  • Work on lab bring up and silicon validation

 

Job Qualifications

  • BS with 8+ years of exp or MS with 6+ years of exp or PhD with 3+ years of exp in Electrical Engineering, Computer Engineering or related equivalent
  • Prior experience in architecting and developing self-checking constrained random verification environment using System Verilog and UVM verification methodology
  • Execution of test plan, debugging failures, write functional coverage objects and review the code coverage and functional coverage with design team
  • Good understanding of object oriented programming concepts
  • Prior experience with PCIE Protocol Gen3 and above
  • Prior experience in verifying is system/sub system level involving multiple blocks
  • Prior experience with protocols such as AXI, APB, AHB etc.
  • Programming in scripting languages like Python, TCL and Perl
  • Excellent communication skills
  • Good problem solving skills and analytical ability
  • Familiarity with EDA tools for simulation, debugging, coverage analysis, CDC, LINT etc.

 

Desirable Qualificaitons

  • Exposure to formal verification methodologies
  • Prior experience with verifying PCIE Bridges with DMA.
  • System level understanding of PCIE based systems
  • Understanding of ARM architecture and assembly language programming
  • Prior experience in integrating Verification IPs (VIP) & UVC in verification environment
  • Prior experience in bringing up gate level simulation and debugging issues.
  • Prior experience with dynamic CDC simulations.
  • Understanding of FPGA architecture
  • Experience with working on Serdes interfaces such as PCIE, Ethernet.

 

#LI-MH2


Requisition Number: 154104 
Country: United States State: California City: San Jose 
Job Function: Design
  

Benefits offered are described here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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