Senior Functional Safety Silicon Design Engineer (166504)

Location: San Jose, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

Senior Functional Safety Silicon Design Engineer (166504)

 

THE ROLE:

AMD-AECG has an opening for a Senior Automotive Functional Safety Silicon Design Engineer in the SOC Functional Safety team. This team is responsible for execution of the Functional Safety Lifecycle for AMD-AECG Adaptive Compute Acceleration Platform (ACAP) including requirements management, safety microarchitecture, safety analyses, and certification.

 

THE PERSON:

Take your ASIC Design, Verification, or Applications background and leverage it into this new and exciting role in automotive functional safety!  In this unique and rapidly growing market opportunity you will develop a rare and highly in demand skillset while improving the lives of others by impacting the functional safety of automobiles!

  

KEY RESPONSIBILITIES:

In this onsite/off-site hybrid role, based in San Jose, CA,  you will contribute across the following diverse set of activities leading to the certification of our ACAP for usage in automotive applications:

  • Requirements management and traceability
  • Review of Safety Concept
  • Specification of Microarchitecture and creation of reusable RTL components for FuSa library
  • Safety Analyses such as DFMEA, DFA and FMEDA on designs that utilize latest technologies from market leaders in ASIC/SOC IP such as Arm
  • Guidance and review of verification, fault injection and validation efforts across block level verif/val teams
  • Preparation of work products for ISO26262 assessments

 

PREFERRED EXPERIENCE:

  • Senior level experience in designing RTL blocks for an SOC, ASIC or FPGA
  • Understanding of safety mechanisms such as Parity, ECC, CRC, Watchdog timer, Voltage/temperature monitoring
  • Basic understanding of synthesis and place & route processes in SOC/ASIC or FPGA design context
  • Experience building testbenches for verification of RTL designs
  • Experience or understanding of fault injection simulations and fault grading
  • Simulation and debugging experience using VCS, IES, Verdi etc
  • Experience with silicon validation of processor based designs
  • Experience in building automation using scripting languages as PERL, Python or TCL
  • Ability to lead others, junior engineers or cross functional teams, through safety analyses 

 

Desired Qualifications

  • Understanding of verification using UVM and pre-silicon validation using prototyping platforms
  • Understanding of design for Functional Safety best practices and knowledge of iSO26262 specific safety analyses
  • Understanding of ARM architecture and APB, AXI, ACE, CHI protocols and network on chip blocks
  • Understanding of common analog blocks such as PLL, ADC, SerDes
  • Understanding of multiple power domains
  • Experience working in design teams distributed over multiple sites
  • Post-silicon validation and debug experience
  • FPGA knowledge and emulation experience
  • Xilinx ISE or Vivado Design Suite and Xilinx Embedded Development Kit

 

ACADEMIC CREDENTIALS:

  • BS or MS (Computer Science, Computer Engineering, Electrical Engineering or related equivalent)

 

LOCATION:

San Jose, CA

 

#LI-AH1


Requisition Number: 166504 
Country: United States State: California City: San Jose 
Job Function: Design
  
Hiring Manager: Sarosh Azad
 

 

Benefits offered are described here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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