MTS Silicon Design Engineer

Location: San Jose, California, US

Company: Advanced Micro Devices

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We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team.

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MTS Silicon Design Engineer-186662




AMD-Xilinx is seeking a capable and motivated RTL/ASIC design engineer to be part of front-end design team of next generation AI Engine/ML processors. You will take part in design and implementation of high-performance, low-power processor and accelerator IP for AI/ML applications.




  • Will define and specify micro-architecture of processor building blocks based on architecture requirementsRTL design and debug of complex blocks in Verilog / System Verilog
  • Analyze performance and make implementation choices to optimize timing
  • Analyze and optimize design for power efficiency and power integrity
  • Work with verification and physical design teams to achieve high quality design and successful tape out
  • Solve customer problems through innovative enhancements to product architecture/ micro-architecture




  • Defining and implementing test plans for the latest software products & features.
  • Creating test accelerated applications to exercise the features under test, these range from simple unit tests to full complex applications
  • Partnering with software development teams to develop tests that target and exercise specific tools features.
  • Analyzing test coverage from functional regressions and closing coverage holes




  • Strong knowledge in following
  • ASIC design flow and direct experience with ASIC design in sub-20nm technology nodes
  • Digital design and experience with RTL design in Verilog/System Verilog
  • Circuit timing/STA, and practical experience with Prime Time or equivalent tools
  • Low power digital design and analysis
  • Experience in following is highly desired
  • Understanding of FPGA architecture and implementation flow
  • Modern SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation
  • TCL, Perl, Python scripting
  • Version control systems such as Perforce, ICManage or Git
  • Strong verbal and written communication skills
  • Ability to organize and present complex technical information
  • Fluent in working with Linux environment



  • BSEE or equivalent and 8 years of relevant work experience, or MSEE or equivalent with 6 years of experience



San Jose, CA



Requisition Number: 186662 
Country: United States State: California City: San Jose 
Job Function: Design

Benefits offered are described here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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