MTS Synthesis, Timing, and Automation Engineer

Location: San Jose, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

MTS Synthesis, Timing, and Automation Engineer

 

Job Description:

AMD is seeking a Staff Synthesis, Timing, and Automation engineer to participate in the development of large SOC’s with multiple physical blocks and 300+ clock domains. As a ‘Middle End’ Design engineer, the candidate will be responsible for development complex multi-mode / multi-block SDC files compatible with both front end and back end flows.  He/She will also define and drive the development of pre-production synthesis (Design Compiler) and STA (Primetime) flows.  Prior experience developing complex TCL scripts in the DC & PT environment is essential.  This experience should include writing custom TCL QC checks as well as writing parsers to extract QC & QoR metrics from standard DC/PT reports.  Also essential is a deep understanding of various synthesis and timing methodologies and their tradeoffs.  The candidate will serve as a methodology lead to drive pre-production front end flows with the CAD team.

 

In addition to developing and maintaining SDC files, the candidate will participate in pre-route timing QC and QoR clean up to eliminate SDC issues and ensure a quality SDC handoff for both pre-route and post-route use.  He/She will also support the RTL design team in the RTL handoff process by running additional QC regressions including LINT, DFT DRC, CDC, RDC, CLP, and Fishtail.  The candidate will be responsible for driving content owners and managing the overall RTL dashboard cleanup for each RTL handoff milestone.

 

The position requires a mix of SDC knowledge, EDA tool competence and TCL-based scripting capability (both in EDA tool environments and stand-alone Linux TCL shell scripts).  Ideal candidates will not only have extensive SDC development and debug experience, but, also have experience cleaning various RTL quality metrics in complex, hierarchical designs and automating that process for improved efficiency.  Familiarity with both front end (RTL) flows and backend (Synthesis and P&R) flows is desired.

High energy candidates with strong written and verbal communication skills, and structured, well-organized work habits are encouraged to apply.

 

Qualifications:

Experience with the following is required:

  • Synopsys: Design Compiler (Logic Synthesis)
  • Synopsys: Primetime (STA)

Experience with any of the following is desired:

  • Synopsys: Spyglass RTL LINT
  • Synopsys: Spyglass RTL DFT
  • Mentor: Questa CDC (Zero In)
  • Mentor: Questa RDC
  • Cadence: Conformal Low Power
  • Fishtail: Confirm

Shell Scripting Experience:

  • Proficient with scripting languages TCL, Perl, Python, CSH
  • Proficient with Cron and LSF job control automation

Academic Credentials:

Bachelor's degree in EE/CE or equivalent field with 8 years of experience, or a Master's degree in EE/CE or equivalent field with 6 years of experience.

 

 

#LI-SB2


Requisition Number: 153789 
Country: United States State: California City: San Jose 
Job Function: Design
  

Benefits offered are described here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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