Standard Cell Library, Sr. Design Engineer (174645)

Location: San Jose, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

Standard Cell Library, Sr. Design Engineer (174645)

 

THE ROLE:

 

We are looking for a Standard Cell Library, Sr. Design Engineer to lead a small a team to cover 16nm, 7nm and 3nm Standard Cell Libraries development, maintenance, and support.

 

THE PERSON:

You should be very familiar with Standard Cell Library development, characterization and QA/release process, basic knowledge of ASIC Synthesis Place & Rout and Cell Based construction flow and VLSI CMOS Circuit/Layout Design knowledge.

 

You should have leadership experience in leading a small team in Library support. Both hands-on and leadership experience in Silicon Development industrial. Easy to work with, good problem-solving skills, positive attitude, responsible and accountable.

 

KEY RESPONSIBILITIES:

  • Planning and defining libraries roadmap & architecture to support internal product development plan and technology roadmap
  • Evaluate, analyze, and maintain 3rd Party Standard Cells Library including download/update, QA and release to the engineering teams
  • Design and generate internal Custom Cell Library. Development includes RTL/Circuit/Layout design and collateral support generation
  • Define and execute characterization, QA and release methodology & flow
  • Support internal engineering for ASIC or Full custom methodology
  • Manage and lead the library team including team build and mentor

 

PREFERRED EXPERIENCE:

  • Expert with Standard Cell Library development
  • Small team leadership experience in Library support
  • Knowledge of CMOS device physics and technology. Understanding of spice netlist and extracted DSPF formats
  • Good understanding of library characterization flow and ED tools & model trade-off
  • Experience in writing checks using scripting languages in perl, tcl
  • Experience in digital implementation design using Synthesis and P&R and Cell Based construction flow
  • Good communication skill with good team spirit. Result oriented

 

ACADEMIC CREDENTIALS:

  • BS or higher in Electrical Engineering or related equivalent

 

LOCATION:

San Jose, CA

 

#LI-AH1

 

Requisition Number: 174645 
Country: United States State: California City: San Jose 
Job Function: Design  

 

Benefits offered are described here, or click on the link,  https://www.amd.com/system/files/documents/us-benefits-at-a-glance-regular-exec-intern-coop.pdf

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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