SMTS IP Silicon Diagnosis Engineer/DFT Engineer

Location: San Jose, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

IP Silicon Diagnosis Engineer/DFT Engineer

 

The Role:

We are looking for a talented and motivated engineer in our advanced debug/diagnosis group. The individual will continually improve and enhance the debug and diagnosis capabilities and will implement new features to support new diagnosis challenges.  Candidate will conduct electrical and physical fault isolation which involves generating diagnosis test patterns and collaborating closely with many other groups such as design, system verification, test engineering and yield.

 

Key Responsibilities :

  • Lead effort to perform electrical and physical fault isolation on first silicon, Yield/QUAL/REL and/or RMA failures
  • Work with production team to make scan test flow diagnosable
  • Build layout database to conduct scan failure diagnosis at physical level
  • Conduct scan diagnosis pattern generation (ATPG) for fault isolation
  • Develop and apply diagnosis patterns for Soft-Defect-Location or Laser-Voltage-Imaging
  • Work with design and DFX team for diagnosable designs

 

Preferred Experience :

  • Knowledge of IC design or verification (RTL, circuit, physical), and semiconductor physics.
  • Experience in IC design, or CAD, scan DFT and ATPG, silicon production validation, characterization or debug/diagnosis.
  • Experience in scan DFT (test compression), TestKompress/TestMAX ATPG, validation and debug/diagnosis.
  • Experience in FPGA (Xilinx Vivado) or any validation tools (VCS, Calibre, Primetime)
  • Familiar with C/C++ or Verilog, fluent in scripting (Perl/python/TCL)
  • Strong problem solving and communication skills with team working spirits, willing to learn new techniques.

 

Academic Credentials:

BS in EE/CE or MS in EE/CE or a related equivalent field.

 

Location:

San Jose, CA

 

#LI-SB2


Requisition Number: 154054 
Country: United States State: California City: San Jose 
Job Function: Process Engineering
  

Benefits offered are described here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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