SOC Verification and Testing Engineer

Location: San Jose, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

SOC Verification and Testing Engineer -  168163

Job Description:

The successful applicant will work as part of the AECG central debug and diagnose team with the responsibility for SOC verification, testing and debug.  Candidate will perform device level and system level verification, validation and debug, both in simulation, emulation and in post-silicon for next generation AMD CPU/GPU/FPGA products. In addition, the candidate will be required to work with cross functional teams such as design, verification and system level test to develop and maintain debug tools, desktop bench, evaluation boards and test plans that facilitate timely SOC failure root causing and functional test coverage goal closure.

 

The candidate needs to have good follow-through and show a commitment to quality. Opportunities to define and implement debug tools, test methodologies and strategies for SOC testing and diagnosis.

 

Responsibilities:

  • Take full ownership of the development and maintenance of diagnostic tools and desktop bench.

  • Participate in SOC system level test work including sub-system and full chip simulation, functional test development, system boot sequence, system level test and functional failure diagnosis

  • Asist in bring-up and test activities for post-silicon validation

  • Maintain and document a library of SOC verification, testing and diagnostics components/tools/evaluation boards targeting AMD products

 

Qualifications: 

  • MS in Electrical Engineering/Computer Science

  • 5 years experience verifying/testing/debugging SOC low level software and hardware issues

  • Strong Verilog/System Verilog skill to understand hardware functionality

  • Be competent to carry out the simulation related work such as testbench setup and waveform based debug

  • Familiar with C low level programming and scripting languages (Python)

  • Strong analytic, communication and teamwork skills

 

Preferred Qualifications:

  • Familiar with ARM processor architecture and Xilinx MicroBlaze

  • ARM SOC pre-silicon simulation and post-silicon validation

  • Experience debugging processor and cache related issues on desktop bench

  • Work experience related to system random test

  • Familiar with system boot sequence such as BSP (Board Supporting Package) and FSBL (First Stage Boot Loader)

  • Experience with embedded software development and debug tools, including compilers, GIT, emulators, UART, JTAG and serial debuggers

  • FPGA design experience with Vivado IP generation

  • Knowledge in fault models such as Stuck-at, Transition, Path Delay, IDDQ, and other models

 

#LI-SB2


Requisition Number: 168163 
Country: United States State: California City: San Jose 
Job Function: Process Engineering
  

Benefits offered are described here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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