Senior Analog Mixed-Signal Design Engineer

Location: San Jose, California, US

Company: Advanced Micro Devices

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At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

Job Description

At AMD/Xilinx, the Analog/Mixed-Signal IP design team is looking for a Circuit Design Engineer to carry out the design and development for the next generation transceiver IOs, high-speed memory (LPDDR5, DDR5, gDDR6, HBM2/HBM3, etc), and chip-to-chip Gbps proprietary PHY IP solutions. As an Analog/Mixed-Signal Designer, your responsibilities include but not limited to the following:

  1. Design and analyze mixed-signal circuit building blocks for PLL, DLL, and clock distribution to be used in the high-speed interfaces
  2. Provide schematic layout guidance to mask designer and perform post-layout simulation
  3. Pre-layout and post-layout design optimization to meet specifications across PVT, sensitivity, aging, electromigration simulation tests
  4. Collaborate with layout engineers, RTL circuit designers to define IP sign-off requirements to ensure efficient IP integration
  5. Define test plans and support for post-silicon IP bring-up, debug, validation and characterization
  6. Interface with SOC teams, system HW/SW teams, and global manufacturing teams to specify component level requirements


Job Qualifications

- BS with 5+ years of exp or MS with 3+ years of exp or PhD in Electrical Engineering, Computer Engineering or related equivalent


  • Experience on Analog/Mixed-Signal circuit design using Cadence Virtuoso design suite tools


  • 2-5 years of relevant design experience in Analog or Digital PLLs/DLL, VCO, TDC and DTC
  • Hand-on design experience in multi-Gbps serial (PCIE, USB, …), parallel high BW memory interface PHY/IOs (DDR4/DDR5, HBM2/HBM3, gDDR5/gDDR6, …) and chip-to-chip links PHY IPs
  • Experience in mixed signal design circuit blocks such as digital/analog DLLs, duty cycle correction, clock and data recovery and clock mixer
  • Experience in low power design techniques for high-speed/custom digital circuit (e.g. CMOS/CML high-speed counters, dividers, …), including transistor level timing sign-off
  • Experience in designing advanced CMOS FinFet process nodes with solid understanding of transistor device level performance characteristics
  • Solid understanding of power, area and performance trade-offs in mixed signal IP designs
  • Proficient in AMS design flows, tools, and methodologies. Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools
  • Excellent written and verbal communication skills, be able to operate without direct supervision, work cross-functionally, cross-geographies collaborating and being part of a multi-disciplinary team in a dynamic/fast-paced environment
  • Exhibit strong initiative and ownership of tasks and responsibilities. Seek help proactively as well as share and pass on knowledge



Requisition Number: 156901 
Country: United States State: California City: San Jose 
Job Function: Design

Benefits offered are described here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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