Senior Clock Design Engineer - Programmable Clock (155661)

Location: San Jose, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

Senior Clock Design Engineer (Programmable Clock) - 155661

 

THE ROLE:

Senior Clock Design Engineer (Programmable Clock) collaborates with the various design team (HW/SW/Architect) to understand and solve the clocking complexity for the FPGA products.

 

The successful candidate will be responsible for Design Implementation of programmable Clock solution and verification to achieve the optimal Power, Performance and Area. Applicants should possess good knowledge about Global Clock design using custom or semi-custom design implementation flow and methodology. Design Challenges involves providing programmable clock implementation solution on 2 & 3D platforms.

 

KEY RESPONSIBILITIES:

  • Investigate Clock architectures and circuits solution, Determine creative design approaches and parameters.
  • Transistor-level design, Circuit design (Clock Design) and layout of high-performance, low-power circuits.
  • Custom and standard cell circuit design, noise mitigation techniques, layout, etc.  
  • Programable global Clock distribution methodologies optimizing Clock - Skew, Jitter, Signal integrity and power integrity issues for 2.5 & 3D platform.

 

PREFERRED EXPERIENCE:

  • Proficient with Cadence custom circuit design tools like ADE-L and ADE-XL and running Monte-Carlo, noise, aging, EM and IR drop simulations and stability analysis.
  • Have good experience with simulation tools such as Spectre, Hspice, AFS, and System Verilog, Python.
  • EDA tools, Design Compiler, ICC2, Primetime and in transistor level analog/mixed signal circuit design. Working knowledge of extraction and STA methodology and tools
  • Coupling, crosstalk delay, effects of process variation, and clock insertion delay effects on timing margins and Clock circuit performance.

 

ACADEMIC CREDENTIALS:

  • Minimum, Bachelor Degree
  • Electrical/Electronic Engineering, Computer Engineering or related equivalent 

 

 

LOCATION:

San Jose, California

 

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Requisition Number: 155661 
Country: United States State: California City: San Jose 
Job Function: Design
  
Hiring Manager: Ashish Akhilesh
 

 

Benefits offered are described here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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