Senior Design Engineer

Location: San Jose, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

Senior Design Engineer


The Role:

The Memory Subsystem team is searching for a passionate, adaptable and innovative design engineer to contribute towards the next generation of HBM PHY and more.


Xilinx has an opening for a Senior Hardware Design Engineer in the IP Design team. This position entails working on digital IC design development of PHY and integration of Memory subsystem blocks for next generation FPGAs. Candidate will support varied aspects of the entire design process including RTL design and functional verification, FE design flows and/or synthesis, timing closure, supporting SW views and working with test engineers on silicon verification and characterization.


Key Responsibilities:

  • The candidate will be responsible for different design stages in the RTL to GDS implementation.

  • The candidate will design, implementation RTL for complex digital and analog blocks using Verilog/System Verilog.

  • The candidate will be responsible for physical design flows (synthesis with DFT) and work on Static Timing Analysis.

  • The candidate will work closely with Functional Verification teams to support block level verification (constrained-random and/or directed verification environments using System Verilog and UVM).

  • The candidate is expected to have strong scripting skills in Perl, Tcl, Shell and/or other languages to support existing & develop new design automation tools/flows for the varied aspects of the design implementation.

  • The candidate is expected to work with various design groups across different disciplines in different geographical locations.

  • The candidate is expected to have regular communication with project teams worldwide to resolve issues and ensure targeted goals.


Preferred Experience:

  • RTL design implementation of Digital blocks using Verilog/System Verilog.

  • Knowledge in VLSI design, Design Automation, IC design.

  • Basic knowledge of EDA Tools (like Synopsys DC Compiler, Primetime, VCS, Cadence Virtuoso).

  • Knowledge of Physical Design (floor planning, synthesis, place & route) and Static Timing Analysis is preferred.

  • Experience with UVM/OVM and/or Verilog, System Verilog test benches, BFMs and usage of simulation tools/debug environments is preferred.

  • Basic understanding of FPGA architecture and customer usage model is a plus.

  • Knowledge of Cadence SPICE, IC compiler is a plus.

  • Experience with Silicon debug/validation at the tested and board level is a plus.

  • Proficiency in Perl, Tcl, Shell, Python and/or other scripting language.

  • Experience creating internal and/or customer facing detailed documentation.

  • Excellent written and verbal communication skills in English.

  • Self-motivated team worker with ability to work in a fast-paced work environment.


Academic Credentials:

BS  or MS or PhD in Electrical Engineering, Computer Engineering or related equivalent



San Jose, CA




Requisition Number: 153422 
Country: United States State: California City: San Jose 
Job Function: Design

Benefits offered are described here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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