Senior Signal Integrity and Power Integrity Engineer

Location: San Jose, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

Job Description

•  Power integrity analysis for die package and PCB, which includes but not limited to layout extraction, electromagnetic and HSPICE simulation to meet silicon noise spec and decoupling strategy and analysis.

•  Simultaneous switching noise/output (SSN or SSO) analysis for I/O power domain.  Eye diagram and jitter analysis via Chip-package-board co-simulation.

•  Optimal layer stackup & power plane assignment to minimize voltage noise.

•  Special noise-sensitive power supply analysis and layout guideline.

•  Signal trace length matching and impact to timing.

•  Crosstalk analysis and reduction.

•  Full-wave simulation and model extraction for signal integrity and power integrity analysis.

 

 

Job Qualifications

•  BS with 5+ years of exp or MS 3+ years of exp or PhD years of exp in Electrical Engineering or Computer Engineering or related equivalent

•  Solid background on transmission line theory and in-depth knowledge of electromagnetics, PCB layout and package layout techniques.

•  Experience with SI simulation tools, e.g.  Synopsis HSPICE, Ansys HFSS, Q3D, Cadence PowerSI, PowerDC, and Agilent ADS.

•  Experience with lab measurements using oscilloscopes, TDRs, VNAs, and spectrum analyzers.

•  Experience in FPGA design is a plus.

•  Self-motivated, teamwork, and good communication skills.

* Understanding system memory IO bus standard - DDR4/5 LPDDR4/5 HBM3 is a plus.

 

 

#LI-MH2

 

 


Requisition Number: 152936 
Country: United States State: California City: San Jose 
Job Function: Design
  

Benefits offered are described here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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