Sr. RTL and Integration Design Engineer - 162221

Location: San Jose, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

AMD has an opening for a Senior RTL and Integration Design Engineer in the SOC Design team. This team is responsible for designing the Processor Sub-system for the Adaptable Compute Acceleration Platform (ACAP).

 

In this highly visible role, you will:

  • Own the design and implementation of blocks to meet functional, timing, area and power requirements
  • Guide and review verification for these blocks
  • Design and implement logic functions that enable efficient test and debug
  • Participate in silicon bring-up for features owned
  • Implement Automation to increase design team efficiency

 

Job Requirement

  • Required Qualifications
    • BSEE with 5 years of experience or MSEE with 3 years of experience or equivalent
    • Experience in designing RTL blocks for an SOC
    • Experience in integrating ASIC IP into SOC
    • Experience writing timing constraints and exceptions in TCL or SDC syntax
    • Experience with automation using scripting techniques such as PERL, Python or TCL
    • Experience running standard quality checks such as Lint and CDC
    • Simulation experience and experience building block level verification suites
    • Experience with synthesis, static timing analysis & optimization
    • Ability to develop clear and concise engineering documentation
    • Ability to lead others, junior engineers or cross functional teams, through complex activities
    • Experience with industry-standard EDA tools from Cadence, Synopsys or Mentor
    • Excellent verbal and written communication skills
    • Excellent organizational skills and attention to detail

 

  • Desired Qualifications
    • Understanding of ARM architecture and APB, AXI, CHI protocols
    • Understanding of coherent mesh network (CMN) designs
    • Understanding of crypto algorithms like AES, SHA, RSA, and ECDSA
    • Understanding of design for security best practices
    • Understanding of design for Functional Safety best practices
    • Experience running automated quality checks on timing constraints
    • Experience designing with multiple power domains including writing UPF
    • MBIST, LBIST, Scan, Scan Compression, ATPG and JTAG design
    • Experience working in design teams distributed over multiple sites
    • Post-silicon validation and debug experience
    • FPGA knowledge and emulation experience
    • Xilinx ISE or Vivado Design Suite and Xilinx Embedded Development Kit


Requisition Number: 162221 
Country: United States State: California City: San Jose 
Job Function: Design
  

Benefits offered are described here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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