Sr. Staff Design Verification Technical Lead Engineer

Location: San Jose, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

Adaptive and Embedded Computing Group (AECG) is looking for a Senior Staff Design Verification Engineer to provide technical leadership and contribution who can provide technical leadership and contribution on Verification of Network-on-Chip (NoC) and high-speed Memory Controller IPs.

The individual will help architect, develop and use simulation and/or formal based verification environments, at block and full-chip level, to prove the functional correctness of Network-on-Chip (NoC), System-level Quality of Service (QoS) and DDR5, LPDDR5, HBM3, RLD, and QDR, Memory Controller IP designs.


The ideal candidate is one who has a proven track record on driving strategies and successful verification execution on Memory Controllers (DDR, LPDDR, RLDRAM, QDR, HBM), high performance IPs, Network-on-Chip and/or SOC designs.


Require hands on experience with verification of state-of-the-art memory controllers such as DDR5, LPDDR5, and HBM2E. Requires strong understanding of current memory controller protocols and calibration (DDR3/4, LPDDR3/4, RLDRAM3, QDR2, QDRIV, HBM-Gen1/2), JEDEC specification, board skew and jitter modeling.


Require proven track record in technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs.


Candidate is expected to be a strong team player with good communication and leadership skills and one who is able to positively and strategically influence the Memory Controller design teams with an eye towards improving overall product quality.


Require BS w/ 8+ yrs or MS w/ 6+ yrs or PhD w/ 4+ yrs in Electrical Engineering, Computer Engineering or Computer Science.


Require experience with development of UVM/OVM and/or Verilog, System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS, Cadence IES to verify memory controller IPs.


Require strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance IP and/or VLSI designs is a plus.


Require familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management.

Experience with FPGA programming and software is a plus.

Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (Magellan / VC Formal) is a plus.

Experience with gate-level simulation, power verification, reset verification, contention checking is a plus.

Experience with silicon debug at the tester and board level, is a plus.

Requisition Number: 169827 
Country: United States State: California City: San Jose 
Job Function: Design

Benefits offered are described here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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