Staff ASIC Design Engineer - AI Engine

Location: San Jose, California, US

Company: Advanced Micro Devices

Apply now

Apply for Job


What you do at AMD changes everything 

We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team.
AMD together we advance_

Staff ASIC Design Engineer - AI Engineer– 152880

 

THE ROLE:

AMD-Xilinx is seeking a capable and motivated RTL/ASIC design engineer to be part of front-end design team of next generation AI Engine/ML processors. 

 

THE PERSON:

 

You will take part in design and implementation of high-performance, low-power processor and accelerator IP for AI/ML applications.

 

KEY RESPONISIBILITES:

In this role you will:

  • Define and specify micro-architecture of processor building blocks based on architecture requirements
  • RTL design and debug of complex blocks in Verilog / System Verilog
  • Analyze performance and make implementation choices to optimize timing
  • Analyze and optimize design for power efficiency and power integrity
  • Work with verification and physical design teams to achieve high quality design and successful tape out
  • Solve customer problems through innovative enhancements to product architecture/ micro-architecture
  • Design and implement underlying clocking infrastructures to ensure implementation tool requirements are met and are optimized for compile time and memory
  • Collaborate with cross-functional teams to solve novel problems across multiple functional areas in development of clocking features and/or algorithms

 

PREFERRED EXPERIECE:

 

Strong experience in the following

  • ASIC design flow and direct experience with ASIC design in sub-20nm technology nodes
  • Digital design and experience with RTL design in Verilog/System Verilog
  • Circuit timing/STA, and practical experience with Prime Time or equivalent tools
  • Low power digital design and analysis
  • Modern SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation

Experience in following is highly desired

  • Understanding of FPGA architecture and implementation flow
  • TCL, Perl, Python scripting
  • Version control systems such as Perforce, ICManage or Git
  • Strong verbal and written communication skills
  • Ability to organize and present complex technical information
  • Fluent in working with Linux environment
  • Needs to be manually updated.

 

ACADEMIC CREDENTIALS

 

BSEE or equivalent and 8 years of relevant work experience, or MSEE or equivalent with 6 years of experience

 

LOCATION:San Jose, CA

 

#LI-DA1

 


Requisition Number: 152880 
Country: United States State: California City: San Jose 
Job Function: Design
  

Benefits offered are described here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

Apply now

Apply for Job

Share this Job