Staff ASIC Design Engineer - AI Engine

Location: San Jose, California, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

Job Description

AMD-Xilinx is seeking a capable and motivated RTL/ASIC design engineer to be part of front end design team of next generation AI Engine/ML processors. You will be take part in design and implementation of high-performance, low-power processor and accelerator IP for AI/ML applications.

 

Job Responsibilities

  • Define and specify micro-architecture of processor building blocks based on architecture requirements
  • RTL design and debug of complex blocks in Verilog / System Verilog
  • Analyze performance and make implementation choices to optimize timing
  • Analyze and optimize design for power efficiency and power integrity
  • Work with verificaton and physical design teams to achieve high quality design and successful tapeout
  • Solve customer problems through innovative enhancements to product architecture/ micro-architecture

Qualifications - Internal

 

Education Requirements

  • BSEE or equivalent and 8 years of relevant work experience, or MSEE or equivalent with 6 years of experience

 

Requirements

  • Strong knowledge in following
    • ASIC design flow and direct experience with ASIC design in sub-20nm technology nodes
    • Digital design and experience with RTL design in Verilog/SystemVerilog
    • Circuit timing/STA, and practical experience with PrimeTime or equivalent tools
    • Low power digital design and analysis
  • Experience in following is highly desired
    • Understanding of FPGA architecture and implementation flow
    • Modern SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation
    • TCL, Perl, Python scripting
    • Version control systems such as Perforce, ICManage or Git
  • Strong verbal and written communication skills
  • Ability to organize and present complex technical information
  • Fluent in working with Linux environment

Needs to be manually updated.


Requisition Number: 152880 
Country: United States State: California City: San Jose 
Job Function: Design
  

Benefits offered are described here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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